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1. 发明授权

US09436626B2 Processor interrupt interface with interrupt partitioning and virtualization enhancements 有权
标题翻译：处理器中断接口具有中断分区和虚拟化增强功能
公开(公告)号：US09436626B2
公开(公告)日：2016-09-06
申请号：US13570874
申请日：2012-08-09
申请人： Bryan D. Marietta , Gary L. Whisenhunt , Kumar K. Gala , David B. Kramer
发明人： Bryan D. Marietta , Gary L. Whisenhunt , Kumar K. Gala , David B. Kramer
IPC分类号： G06F13/26 , G06F9/50 , G06F9/45 , G06F13/14 , G06F13/24 , G06F9/455
CPC分类号： G06F13/26 , G06F9/45533 , G06F9/5077 , G06F13/14 , G06F13/24
摘要： A method and circuit for a data processing system (200) provide a processor-based partitioned priority blocking mechanism by storing interrupt identifiers, partition identifiers, thread identifiers, and priority levels associated with accepted interrupt requests in special purpose registers (35-38) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.
摘要翻译：用于数据处理系统（200）的方法和电路通过将所接收的中断请求相关联的中断标识符，分区标识符，线程标识符和优先权级别存储在位于专用寄存器（35-38）中来提供基于处理器的分区优先级阻塞机制在处理器核心（26）上，以便在分区的基础上实现快速有效的中断优先级阻塞。

2. 发明授权

US09395983B2 Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operation 有权
标题翻译：调试指令由第一个线程执行以在第二个线程中生成调试事件以导致暂停操作
公开(公告)号：US09395983B2
公开(公告)日：2016-07-19
申请号：US12195220
申请日：2008-08-20
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30 , G06F11/36
CPC分类号： G06F9/3005 , G06F9/3009 , G06F11/3648
摘要： For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug related instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread, wherein processing the debug event comprises causing a halting operation related to the processor.
摘要翻译：为了在包括处理器的数据处理系统中使用，该处理器被配置为执行对应于第一线程的第一组指令和对应于第二线程的第二组指令，提供了一种方法。该方法包括响应于在执行第一组指令时由第一线程执行与调试相关的指令，生成用于由第二线程处理的调试事件，其中处理调试事件包括引起与处理器相关的暂停操作。

3. 发明授权

US09229884B2 Virtualized instruction extensions for system partitioning 有权
标题翻译：用于系统分区的虚拟化指令扩展
公开(公告)号：US09229884B2
公开(公告)日：2016-01-05
申请号：US13460287
申请日：2012-04-30
申请人： Bryan D. Marietta , Gary L. Whisenhunt , Kumar K. Gala , David B. Kramer
发明人： Bryan D. Marietta , Gary L. Whisenhunt , Kumar K. Gala , David B. Kramer
IPC分类号： G06F13/24 , G06F13/14
CPC分类号： G06F13/14
摘要： A method and circuit for a data processing system provide virtualized instructions for accessing a partitioned device (e.g., 14, 61) by executing a control instruction (47, 48) to encode and store an access command (CMD) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register (25) at a physical address (PA) retrieved from a special purpose register (46) so that the partitioned device (14, 61) can determine if the access command can be performed based on local access control information.
摘要翻译：用于数据处理系统的方法和电路通过执行控制指令（47,48）来提供用于访问分区设备（例如，14,61）的虚拟化指令，以将数据有效载荷中的访问命令（CMD）编码和存储在硬件插入分区属性（LPID），用于存储到从专用寄存器（46）检索的物理地址（PA）处的命令寄存器（25），使得分区设备（14,61）可以确定访问命令是否可以基于本地访问控制信息执行。

4. 发明申请

US20100125750A1 PROGRAMMABLE ERROR ACTIONS FOR A CACHE IN A DATA PROCESSING SYSTEM 有权
标题翻译：数据处理系统中缓存的可编程错误操作
公开(公告)号：US20100125750A1
公开(公告)日：2010-05-20
申请号：US12273155
申请日：2008-11-18
申请人： William C. Moyer , Gary L. Whisenhunt
发明人： William C. Moyer , Gary L. Whisenhunt
IPC分类号： G06F11/20
CPC分类号： G06F11/0793 , G06F11/073 , G06F12/0802
摘要： A data processing system and method of operation has a processor coupled to a cache. Cache control circuitry is coupled to the cache and performs error detection. A user programmable error action control register stores a control value for selecting a type of error action to be taken when a cache error is detected. A first value of the control value permits handling of a cache error that is transparent to the processor, and a second value permits handling of the cache error by taking an exception that is visible to the processor. Various alternate actions to a detected error, including error correction or cache line invalidation, may be taken in response to other values of the control value.
摘要翻译：数据处理系统和操作方法具有耦合到高速缓存的处理器。缓存控制电路耦合到高速缓存并执行错误检测。用户可编程错误动作控制寄存器存储用于选择检测到高速缓存错误时要采取的错误动作的类型的控制值。控制值的第一个值允许处理对处理器透明的高速缓存错误，第二个值允许通过处理器可见的异常来处理高速缓存错误。响应于控制值的其他值，可以采取针对检测到的错误的各种替代动作，包括纠错或高速缓存线无效。

5. 发明授权

US07584344B2 Instruction for conditionally yielding to a ready thread based on priority criteria 有权
标题翻译：根据优先级标准有条件地屈服于准备好的线程的指令
公开(公告)号：US07584344B2
公开(公告)日：2009-09-01
申请号：US11381284
申请日：2006-05-02
申请人： William C. Moyer , Gary L. Whisenhunt
发明人： William C. Moyer , Gary L. Whisenhunt
IPC分类号： G06F9/40
CPC分类号： G06F9/4843 , G06F2209/507
摘要： An integrated circuit (10) has a conditional yield instruction (305) which may be used to conditionally yield execution of a currently active thread based on priority and status of other threads. In one embodiment, an I bit 304 may be used to designate whether the priority selection bits (50) are stored in the instruction itself. If the priority selection bits (50) are not stored in the instruction itself, a portion of the instruction (302) may be used to store a location indicator which indicates where the priority selection bits (50) are located (e.g. register file 22).
摘要翻译：集成电路（10）具有条件收益率指令（305），其可以用于基于其他线程的优先级和状态有条件地产生当前活动线程的执行。在一个实施例中，可以使用I比特304来指示优先权选择比特（50）是否被存储在指令本身中。如果优先级选择位（50）未被存储在指令本身中，则指令（302）的一部分可以用于存储指示优先级选择位（50）所在位置的位置指示符（例如寄存器文件22）。

6. 发明授权

US09213665B2 Data processor for processing a decorated storage notify 有权
标题翻译：用于处理装饰存储的数据处理器通知
公开(公告)号：US09213665B2
公开(公告)日：2015-12-15
申请号：US12259368
申请日：2008-10-28
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F12/02 , G06F13/42 , G06F13/16 , G06F9/30 , G06F9/38
CPC分类号： G06F13/4217 , G06F9/3004 , G06F9/30043 , G06F9/3834 , G06F9/3885 , G06F13/16 , G06F2213/0054
摘要： A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. A decorated storage notify (DSN) transaction includes an indication of an instruction operation, an address associated with the instruction operation, and a decoration value (i.e. a command to the target device to perform a function in addition to a store or a load). The transaction on the system interconnect includes an address phase and no data phase, thereby improving system bandwidth. In one form the target device (e.g. a memory with functionality in addition to storage functionality) performs a read-modify-write operation using information at a storage location of the target device.
摘要翻译：具有处理器和目标设备的数据处理系统处理装饰指令（即具有装饰值的指令）。诸如处理器之类的数据处理系统的设备通过系统互连将事务发送到目标设备。装饰存储通知（DSN）事务包括指令操作的指示，与指令操作相关联的地址和装饰值（即，除了存储或负载之外还执行功能的目标设备的命令）。系统互连上的事务包括地址阶段和数据阶段，从而提高系统带宽。在一种形式中，目标设备（例如具有除了存储功能之外的功能的存储器）使用目标设备的存储位置处的信息执行读取 - 修改 - 写入操作。

7. 发明授权

US09152587B2 Virtualized interrupt delay mechanism 有权
标题翻译：虚拟化中断延迟机制
公开(公告)号：US09152587B2
公开(公告)日：2015-10-06
申请号：US13485120
申请日：2012-05-31
申请人： Bryan D. Marietta , Gary L. Whisenhunt , Kumar K. Gala , David B. Kramer
发明人： Bryan D. Marietta , Gary L. Whisenhunt , Kumar K. Gala , David B. Kramer
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A method and circuit for a data processing system provide a partitioned interrupt controller with an efficient deferral mechanism for processing partitioned interrupt requests by executing a control instruction to encode and store a delay command (e.g., DEFER or SUSPEND) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register (25) at a physical address (PA) retrieved from a special purpose register (46) so that the partitioned interrupt controller (14) can determine if the delay command can be performed based on local access control information.
摘要翻译：一种用于数据处理系统的方法和电路，通过执行控制指令来编码和存储具有硬件的数据有效载荷中的延迟命令（例如，DEFER或SUSPEND）来提供具有用于处理分区中断请求的有效延迟机制的分区中断控制器 - 插入分区属性（LPID），用于存储到从专用寄存器（46）检索的物理地址（PA）处的命令寄存器（25），使得分区中断控制器（14）可以确定是否可以执行延迟命令基于本地访问控制信息。

8. 发明申请

US20140047150A1 Processor Interrupt Interface with Interrupt Partitioning and Virtualization Enhancements 有权
标题翻译：具有中断分区和虚拟化增强功能的处理器中断接口
公开(公告)号：US20140047150A1
公开(公告)日：2014-02-13
申请号：US13570874
申请日：2012-08-09
申请人： Bryan D. Marietta , Gary L. Whisenhunt , Kumar K. Gala , David B. Kramer
发明人： Bryan D. Marietta , Gary L. Whisenhunt , Kumar K. Gala , David B. Kramer
IPC分类号： G06F13/26
CPC分类号： G06F13/26 , G06F9/45533 , G06F9/5077 , G06F13/14 , G06F13/24
摘要： A method and circuit for a data processing system (200) provide a processor-based partitioned priority blocking mechanism by storing interrupt identifiers, partition identifiers, thread identifiers, and priority levels associated with accepted interrupt requests in special purpose registers (35-38) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.
摘要翻译：用于数据处理系统（200）的方法和电路通过将所接收的中断请求相关联的中断标识符，分区标识符，线程标识符和优先级级别存储在位于专用寄存器（35-38）中来提供基于处理器的分区优先级阻塞机制在处理器核心（26）上，以便在分区的基础上实现快速有效的中断优先级阻塞。

9. 发明授权

US07941499B2 Interprocessor message transmission via coherency-based interconnect 有权
标题翻译：通过基于相干性互连的处理器间消息传输
公开(公告)号：US07941499B2
公开(公告)日：2011-05-10
申请号：US11682867
申请日：2007-03-06
申请人： Becky G. Bruce , Sanjay R. Deshpande , Michael D. Snyder , Gary L. Whisenhunt , Kumar Gala
发明人： Becky G. Bruce , Sanjay R. Deshpande , Michael D. Snyder , Gary L. Whisenhunt , Kumar Gala
IPC分类号： G06F15/167
CPC分类号： G06F15/16 , G06F9/546 , G06F12/0833
摘要： A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages.
摘要翻译：一种方法包括经由一致性互连在多处理器系统的处理器之间传送第一消息，由此第一消息包括一致性信息。该方法还包括经由一致性互连在多处理器系统的处理器之间传送第二消息，由此第二消息包括处理器内消息信息。系统包括一致性互连和处理器。处理器包括被配置为从一致性互连接收消息的接口，每个消息包括一致性信息或处理器间消息信息之一。该处理器还包括一个相关性管理模块，被配置为处理从至少一个消息获得的一致性信息，以及中断控制器，该中断控制器被配置为基于从至少一个消息获得的处理器间消息信息来生成中断。

10. 发明授权

US07849247B2 Interrupt controller for accelerated interrupt handling in a data processing system and method thereof 有权
标题翻译：用于数据处理系统中加速中断处理的中断控制器及其方法
公开(公告)号：US07849247B2
公开(公告)日：2010-12-07
申请号：US12250682
申请日：2008-10-14
申请人： Bryan D. Marietta , Michael D. Snyder , Gary L. Whisenhunt , Daniel L. Bouvier
发明人： Bryan D. Marietta , Michael D. Snyder , Gary L. Whisenhunt , Daniel L. Bouvier
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.
摘要翻译：数据处理系统具有中断控制器，其向处理器提供中断请求以及对应的中断标识符和相应的中断向量。如果处理器接受中断，处理器将通过中断标识符和中断确认返回相同的中断标识符值给中断控制器。还可以提供中断/未采取的指示符。用于协调中断控制器和处理器之间的中断处理的通信接口可能是异步的。

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