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1. 发明授权

US07528438B2 Non-volatile memory including assist gate 有权
标题翻译：包括辅助门的非易失性存储器
公开(公告)号：US07528438B2
公开(公告)日：2009-05-05
申请号：US11162035
申请日：2005-08-26
申请人： Ko-Hsing Chang , Chiu-Tsung Huang
发明人： Ko-Hsing Chang , Chiu-Tsung Huang
IPC分类号： H01L29/788 , H01L29/76
CPC分类号： G11C16/0491 , G11C16/0425 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： A non-volatile memory is provided. An assist gate structure is formed on a substrate such that the width at the bottom of the assist gate structure is greater than the width at the top of the assist gate structure. A floating gate is formed on one side of the assist gate structure and disposed between a word line and the substrate. The width at the bottom of the floating gate is smaller than the width at the top of the floating gate. The word line, the floating gate and the assist gate structure together form a memory unit. A tunneling dielectric layer is formed between the floating gate and the substrate. An inter-gate dielectric layer is formed between the word line, the floating gate and the assist gate structure. Source/drain regions are formed in the substrate on the respective sides of the memory unit.
摘要翻译：提供非易失性存储器。辅助栅极结构形成在基板上，使得辅助栅极结构底部的宽度大于辅助栅极结构顶部的宽度。浮动栅极形成在辅助栅极结构的一侧并且设置在字线和基板之间。浮动栅极底部的宽度小于浮动栅极顶部的宽度。字线，浮栅和辅助栅结构一起形成存储单元。在浮动栅极和衬底之间形成隧穿电介质层。在字线，浮栅和辅助栅结构之间形成栅极间电介质层。源极/漏极区域形成在存储器单元的相应侧上的衬底中。

2. 发明授权

US07446370B2 Non-volatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US07446370B2
公开(公告)日：2008-11-04
申请号：US11308667
申请日：2006-04-20
申请人： Ko-Hsing Chang , Tsung-Cheng Huang , Yan-Hung Huang
发明人： Ko-Hsing Chang , Tsung-Cheng Huang , Yan-Hung Huang
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： A non-volatile memory is provided, including a substrate, a control gate, a floating gate, and a select gate. A source region and a drain region are disposed in the substrate. The control gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed between the control gate and the substrate. The cross-section of the floating gate presents, for example, an L-shape and the floating gate includes a central region which is perpendicular to the substrate and a lateral region which is parallel to the substrate. The central region is adjacent to the source region. The select gate is disposed on the sidewall of the control gate and the lateral region of the floating gate, and is adjacent to the drain region. Besides, the present invention further includes a method of manufacturing the above non-volatile memory.
摘要翻译：提供了一种非易失性存储器，包括基板，控制栅极，浮动栅极和选择栅极。源极区域和漏极区域设置在衬底中。控制栅极设置在源极区域和漏极区域之间的衬底上。浮栅设置在控制栅极和衬底之间。浮动栅极的横截面呈现例如L形，并且浮动栅极包括垂直于衬底的中心区域和平行于衬底的横向区域。中心区域与源区域相邻。选择栅极设置在控制栅极的侧壁和浮置栅极的横向区域上，并且与漏极区域相邻。此外，本发明还包括制造上述非易失性存储器的方法。

3. 发明申请

US20080035981A1 ONE TIME PROGRAMMABLE MEMORY AND THE MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：一次性可编程存储器及其制造方法
公开(公告)号：US20080035981A1
公开(公告)日：2008-02-14
申请号：US11309444
申请日：2006-08-08
申请人： Ko-Hsing Chang , Su-Yuan Chang
发明人： Ko-Hsing Chang , Su-Yuan Chang
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11556 , H01L29/42336 , H01L29/7881
摘要： A one time programmable memory including a first memory cell is provided. The first memory cell is disposed on a substrate having a trench disposed therein. The first memory cell includes a floating gate, a select gate, a first doped region, a second doped region and a third doped region. The floating gate is disposed on the sidewall of the trench. The select gate is disposed on the substrate outside the trench. The first doped region is disposed in the substrate at the bottom of the trench. The second and third doped regions are disposed in the substrate on both sides of the trench, and the second doped region is disposed between the floating gate and the select gate.
摘要翻译：提供了包括第一存储单元的一次可编程存储器。第一存储单元设置在其中布置有沟槽的衬底上。第一存储单元包括浮置栅极，选择栅极，第一掺杂区域，第二掺杂区域和第三掺杂区域。浮栅设置在沟槽的侧壁上。选择栅极设置在沟槽外部的衬底上。第一掺杂区域设置在沟槽底部的衬底中。第二和第三掺杂区域设置在沟槽两侧的衬底中，并且第二掺杂区域设置在浮置栅极和选择栅极之间。

4. 发明申请

US20070262368A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20070262368A1
公开(公告)日：2007-11-15
申请号：US11308667
申请日：2006-04-20
申请人： Ko-Hsing Chang , Tsung-Cheng Huang , Yan-Hung Huang
发明人： Ko-Hsing Chang , Tsung-Cheng Huang , Yan-Hung Huang
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： A non-volatile memory is provided, including a substrate, a control gate, a floating gate, and a select gate. A source region and a drain region are disposed in the substrate. The control gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed between the control gate and the substrate. The cross-section of the floating gate presents, for example, an L-shape and the floating gate includes a central region which is perpendicular to the substrate and a lateral region which is parallel to the substrate. The central region is adjacent to the source region. The select gate is disposed on the sidewall of the control gate and the lateral region of the floating gate, and is adjacent to the drain region. Besides, the present invention further includes a method of manufacturing the above non-volatile memory.
摘要翻译：提供了一种非易失性存储器，包括基板，控制栅极，浮动栅极和选择栅极。源极区域和漏极区域设置在衬底中。控制栅极设置在源极区域和漏极区域之间的衬底上。浮栅设置在控制栅极和衬底之间。浮动栅极的横截面呈现例如L形，并且浮动栅极包括垂直于衬底的中心区域和平行于衬底的横向区域。中心区域与源区域相邻。选择栅极设置在控制栅极的侧壁和浮置栅极的横向区域上，并且与漏极区域相邻。此外，本发明还包括制造上述非易失性存储器的方法。

5. 发明申请

US20060186459A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20060186459A1
公开(公告)日：2006-08-24
申请号：US11162035
申请日：2005-08-26
申请人： Ko-Hsing Chang , Chiu-Tsung Huang
发明人： Ko-Hsing Chang , Chiu-Tsung Huang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： G11C16/0491 , G11C16/0425 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： A non-volatile memory is provided. An assist gate structure is formed on a substrate such that the width at the bottom of the assist gate structure is greater than the width at the top of the assist gate structure. A floating gate is formed on one side of the assist gate structure and disposed between a word line and the substrate. The width at the bottom of the floating gate is smaller than the width at the top of the floating gate. The word line, the floating gate and the assist gate structure together form a memory unit. A tunneling dielectric layer is formed between the floating gate and the substrate. An inter-gate dielectric layer is formed between the word line, the floating gate and the assist gate structure. Source/drain regions are formed in the substrate on the respective sides of the memory unit.
摘要翻译：提供非易失性存储器。辅助栅极结构形成在基板上，使得辅助栅极结构底部的宽度大于辅助栅极结构顶部的宽度。浮动栅极形成在辅助栅极结构的一侧并且设置在字线和基板之间。浮动栅极底部的宽度小于浮动栅极顶部的宽度。字线，浮栅和辅助栅结构一起形成存储单元。在浮动栅极和衬底之间形成隧穿电介质层。在字线，浮栅和辅助栅结构之间形成栅极间电介质层。源极/漏极区域形成在存储器单元的相应侧上的衬底中。

6. 发明授权

US07049189B2 Method of fabricating non-volatile memory cell adapted for integration of devices and for multiple read/write operations 失效
标题翻译：制造非易失性存储单元的方法，适用于器件集成和多重读/写操作
公开(公告)号：US07049189B2
公开(公告)日：2006-05-23
申请号：US10708904
申请日：2004-03-31
申请人： Ko-Hsing Chang , Su-Yuan Chang
发明人： Ko-Hsing Chang , Su-Yuan Chang
IPC分类号： H01L21/8238
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/7923
摘要： A method of manufacturing a non-volatile memory cell includes forming a bottom dielectric layer and a charge trapping layer on a substrate sequentially. The electron trapping layer is patterned to form a trench exposing a portion of the bottom dielectric layer. A top dielectric layer is formed over the substrate and covers the electron trapping layer and the exposed bottom dielectric layer. A conductive layer is then formed on the top dielectric layer. The conductive layer, the top dielectric layer, the electron trapping layer and the bottom dielectric layer are patterned to form a stacked structure, wherein a width of the stacked structure is larger than a width of the trench. A source/drain region is formed in the substrate adjacent to the edges of the stacked structure. Because the electron trapping layer of the memory cell is divided into two isolation structures according to the invention, it is adapted for the integration of devices and for long-time operation.
摘要翻译：制造非易失性存储单元的方法包括依次在衬底上形成底部电介质层和电荷俘获层。图案化电子俘获层以形成露出底部电介质层的一部分的沟槽。顶部电介质层形成在衬底上并覆盖电子俘获层和暴露的底部介电层。然后在顶部介电层上形成导电层。将导电层，顶部电介质层，电子俘获层和底部电介质层图案化以形成堆叠结构，其中层叠结构的宽度大于沟槽的宽度。源极/漏极区域形成在与层叠结构的边缘相邻的衬底中。因为根据本发明的存储器单元的电子俘获层被分成两个隔离结构，所以适用于器件的集成和长时间的操作。

7. 发明授权

US06737700B1 Non-volatile memory cell structure and method for manufacturing thereof 有权
标题翻译：非易失性存储单元结构及其制造方法
公开(公告)号：US06737700B1
公开(公告)日：2004-05-18
申请号：US10249864
申请日：2003-05-13
申请人： Ko-Hsing Chang , Cheng-Yuan Hsu
发明人： Ko-Hsing Chang , Cheng-Yuan Hsu
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A non-volatile memory cell having a symmetric cell structure is disclosed. The non-volatile memory cell includes a substrate, a tunnel oxide layer, two floating gates, a dielectric layer, a plurality of spacers, a control gate, and two split gates. The substrate has at least two sources and a drain that is located between the sources. The floating gates are formed on the tunneling oxide layer, and each of floating gates is located between each source and the drain. The dielectric layer is formed on the floating gates. The control gate is formed over the drain and is between the floating gates. The split gates are located adjacent to outward sidewalls of the floating gates, respectively. Therefore, each of the split gates is opposite to the control gate through each of the floating gates.
摘要翻译：公开了具有对称单元结构的非易失性存储单元。非易失性存储单元包括衬底，隧道氧化物层，两个浮动栅极，电介质层，多个间隔物，控制栅极和两个分离栅极。衬底具有至少两个源和位于源之间的漏极。浮动栅极形成在隧道氧化物层上，每个浮栅位于每个源极和漏极之间。电介质层形成在浮栅上。控制栅极形成在漏极之上并且在浮动栅极之间。分流门分别位于浮动门的外侧壁附近。因此，每个分离门通过每个浮动栅极与控制栅极相对。

8. 发明授权

US07394126B2 Non-volatile memory and manufacturing method thereof 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US07394126B2
公开(公告)日：2008-07-01
申请号：US11308717
申请日：2006-04-26
申请人： Ko-Hsing Chang , Su-Yuan Chang
发明人： Ko-Hsing Chang , Su-Yuan Chang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42324
摘要： A non-volatile memory is described, including a substrate, a floating gate, a control gate, a source region, and a drain region. A trench is disposed in the substrate, and a step-like recess is located in the substrate beside the trench. The floating gate is disposed on the sidewall of the trench. The control gate is disposed on the substrate between the trench and the step-like recess which extends in the step-like recess. The source region is disposed in the substrate at the bottom of the trench. The drain region is disposed in the substrate at the bottom of the step-like recess.
摘要翻译：描述了非易失性存储器，包括衬底，浮置栅极，控制栅极，源极区域和漏极区域。沟槽设置在衬底中，并且阶梯状凹部位于沟槽旁边的衬底中。浮栅设置在沟槽的侧壁上。控制栅极设置在沟槽与阶梯状凹部之间延伸的台阶状凹部之间的基板上。源极区域设置在沟槽底部的衬底中。漏极区域设置在台阶状凹部的底部的基板中。

9. 发明授权

US07208796B2 Split gate flash memory 失效
标题翻译：分闸门闪存
公开(公告)号：US07208796B2
公开(公告)日：2007-04-24
申请号：US11163223
申请日：2005-10-11
申请人： Ko-Hsing Chang , Wu-Tsung Chung , Tsung-Cheng Huang
发明人： Ko-Hsing Chang , Wu-Tsung Chung , Tsung-Cheng Huang
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/7885
摘要： A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling dielectric layer, a floating gate and a cap layer are formed on the active layers. The inter-gate dielectric layers are formed on the sidewalls of the stacked gate structures. The select gates are formed on one side of the stacked gate structure and across the active layer. The select gate dielectric layers are formed between the select gates and the active layers. The source regions are formed in the active layers on the other side of the stacked gate structures. The drain regions are formed in the active layers on one side of the select gates.
摘要翻译：提供了分闸门闪存。在衬底中形成沟槽以限定活性层。器件隔离层形成在沟槽中。器件隔离层的表面低于有源层的表面。在有源层上形成各自包括隧道电介质层，浮栅和覆盖层的层叠栅极结构。栅极间电介质层形成在堆叠的栅极结构的侧壁上。选择栅极形成在层叠的栅极结构的一侧并跨越有源层。选择栅极电介质层形成在选择栅极和有源层之间。源极区域形成在堆叠栅极结构的另一侧上的有源层中。漏极区域形成在选择栅极一侧的有源层中。

10. 发明申请

US20070048961A1 SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070048961A1
公开(公告)日：2007-03-01
申请号：US11306897
申请日：2006-01-16
申请人： Ko-Hsing Chang , Wu-Tsung Chung , Tsung-Yu Lee
发明人： Ko-Hsing Chang , Wu-Tsung Chung , Tsung-Yu Lee
IPC分类号： H01L21/20
CPC分类号： H01L29/66545 , H01L21/26586 , H01L21/28114 , H01L29/1083 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： A semiconductor device and fabricating method thereof are provided. In the fabricating method, two trenches are formed in the substrate and, then the first dielectric layers is formed on the sidewalls of the trenches and a source/drain layer is formed in each trench. A second dielectric layer is formed on the substrate and the source/drain layer. Finally, a gate structure is formed on the second dielectric layer. The source/drain layers and the first dielectric layers are placed in trenches; therefore, device dimension can be reduced.
摘要翻译：提供了一种半导体器件及其制造方法。在制造方法中，在衬底中形成两个沟槽，然后在沟槽的侧壁上形成第一电介质层，并且在每个沟槽中形成源极/漏极层。在基板和源极/漏极层上形成第二电介质层。最后，在第二电介质层上形成栅极结构。源极/漏极层和第一电介质层被放置在沟槽中; 因此，可以减少设备尺寸。

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