专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4700455A Method of fabricating Schottky gate-type GaAs field effect transistor 失效
标题翻译：制造肖特基栅型GaAs场效应晶体管的方法
公开(公告)号：US4700455A
公开(公告)日：1987-10-20
申请号：US792825
申请日：1985-10-30
申请人： Kizashi Shimada , Tatsuo Akiyama , Yutaka Koshino
发明人： Kizashi Shimada , Tatsuo Akiyama , Yutaka Koshino
IPC分类号： H01L21/338 , H01L29/812 , H01L21/265
CPC分类号： H01L29/66878 , H01L29/812
摘要： A method of manufacturing a semiconductor device wherein an insulating film of silicon dioxide is provided on the sidewalls of a gate electrode. This silicon dioxide film is used to define the length of the gate region during formation of the source and drain regions by ion implantation, and to accurately position the gate electrode relative to the source and drain regions.
摘要翻译：一种制造半导体器件的方法，其中二极管的绝缘膜设置在栅电极的侧壁上。该二氧化硅膜用于通过离子注入来形成源极和漏极区域期间限定栅极区域的长度，并且相对于源极和漏极区域精确地定位栅电极。

2. 发明授权

US5229323A Method for manufacturing a semiconductor device with Schottky electrodes 失效
标题翻译：制造具有肖特基电极的半导体器件的方法
公开(公告)号：US5229323A
公开(公告)日：1993-07-20
申请号：US846985
申请日：1992-03-09
申请人： Kizashi Shimada , Tatsuo Akiyama , Yutaka Koshino
发明人： Kizashi Shimada , Tatsuo Akiyama , Yutaka Koshino
IPC分类号： H01L21/263 , H01L21/285 , H01L21/338
CPC分类号： H01L29/66863 , H01L21/2633 , H01L21/28581 , Y10S148/139 , Y10S148/14
摘要： A method for manufacturing a semiconductor device with a Schottky electrode includes the steps of subjecting the surface of a GaAs substrate to a sputtering etching process in a sputtering processing chamber of a sputtering device; and depositing Schottky electrode material by sputtering on the surface of the substrate to form a Schottky electrode in the processing chamber without exposing the substrate to the atmosphere.
摘要翻译：制造具有肖特基电极的半导体器件的方法包括以下步骤：在溅射装置的溅射处理室中对GaAs衬底的表面进行溅射蚀刻工艺; 并通过溅射将肖特基电极材料沉积在衬底的表面上以在处理室中形成肖特基电极，而不将衬底暴露于大气中。

3. 发明授权

US5049954A GaAs field effect semiconductor device having Schottky gate structure 失效
标题翻译：具有肖特基门结构的GaAs场效应半导体器件
公开(公告)号：US5049954A
公开(公告)日：1991-09-17
申请号：US446467
申请日：1989-12-05
申请人： Kizashi Shimada , Tatsuo Akiyama , Yutaka Koshino
发明人： Kizashi Shimada , Tatsuo Akiyama , Yutaka Koshino
IPC分类号： H01L21/338 , H01L21/28 , H01L29/417 , H01L29/43 , H01L29/47 , H01L29/812
CPC分类号： H01L29/475
摘要： A Schottky gate electrode structure of a GaAs field effect semiconductor device comprises a Ti film having a thickness of 2 nm to 25 nm and provided adherently on a GaAs substrate including source and drain regions, and a refractory electrode film provided on the Ti film and formed of a material selected from W, Mo, Cr, Ta, Nb, V, Hf, Zr, nitrides of these metals, silicides of these metals, carbides of these metals, Ti-W alloys, WSixNy, TiNx, and TiSix. Adhesion of the refractory electrode film to the GaAs substrate is increased, and heat resisting properties of Schottky characteristics are improved according to the thin Ti film.

4. 发明授权

US5031021A Semiconductor device with a high breakdown voltage 失效
标题翻译：具有高击穿电压的半导体器件
公开(公告)号：US5031021A
公开(公告)日：1991-07-09
申请号：US905958
申请日：1986-09-11
申请人： Yoshiro Baba , Kazuo Tsuru , Tatsuo Akiyama , Yutaka Koshino
发明人： Yoshiro Baba , Kazuo Tsuru , Tatsuo Akiyama , Yutaka Koshino
IPC分类号： H01L29/73 , H01L21/331 , H01L29/04 , H01L29/06 , H01L29/40 , H01L29/732
CPC分类号： H01L29/405 , H01L29/04 , H01L29/0619 , H01L29/408
摘要： There is disclosed a power transistor comprising a semiconductor substrate having a PN junction exposed on a major surface of the semiconductor substrate, and a semiinsulative polysilicon film formed on the major surface, the polysilicon film covering the PN junction, the polysilicon film containing at least one of carbon, oxygen, and nitrogen, and the polysilicon film having a thickness of about 3000 .ANG..
摘要翻译：公开了一种功率晶体管，其包括具有在该半导体衬底的主表面上露出的PN结的半导体衬底和形成在该主表面上的半绝缘性多晶硅膜，该多晶硅膜覆盖该PN结，该多晶硅膜含有至少一个的碳，氧和氮，以及多晶硅膜的厚度约为3000纳米。

5. 发明授权

US4729966A Process for manufacturing a Schottky FET device using metal sidewalls as gates 失效
标题翻译：使用金属侧壁作为栅极制造肖特基FET器件的工艺
公开(公告)号：US4729966A
公开(公告)日：1988-03-08
申请号：US843833
申请日：1986-03-26
申请人： Yutaka Koshino , Tatsuo Akiyama , Shunichi Hiraki
发明人： Yutaka Koshino , Tatsuo Akiyama , Shunichi Hiraki
IPC分类号： H01L29/812 , H01L21/28 , H01L21/285 , H01L21/338 , H01L29/417 , H01L21/225 , H01L29/72 , H01L29/80
CPC分类号： H01L29/66878 , H01L21/2815 , H01L21/28587
摘要： A first insulative film is formed with predetermined height and thickness in a loop shape on the surface of the Schottky-junction semiconductor substrate. A gate electrode metal film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the first insulative film. A second insulative film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the metal film. A channel consisting of a low concentration impurity layer, is formed in a loop shape inside the substrate directly under the metal film and the first and second insulative films. The source region consists of a high-concentration impurity layer formed such that it surrounds the channel positioned inside the substrate on the outside of the first insulative film. The drain region consists of a high-concentration impurity layer, which is formed such that it is surrounded by the channel positioned inside the substrate on the inside of the second insulative film.
摘要翻译：第一绝缘膜在肖特基结半导体衬底的表面上以环形形成预定的高度和厚度。栅极电极金属膜沿着第一绝缘膜的内表面在基板的表面上以环形形成预定的高度和厚度。第二绝缘膜沿着金属膜的内表面在基板的表面上以环形形成预定的高度和厚度。由低浓度杂质层构成的通道在金属膜正下方的基板内部以及第一绝缘膜和第二绝缘膜之间形成为环状。源极区域由高浓度杂质层构成，其形成为使得其围绕位于第一绝缘膜外侧的衬底内的沟道。漏极区域由高浓度杂质层构成，其形成为被位于第二绝缘膜内侧的位于基板内部的沟道包围。

6. 发明授权

US4532004A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4532004A
公开(公告)日：1985-07-30
申请号：US636221
申请日：1984-07-31
申请人： Tatsuo Akiyama , Yutaka Koshino , Shunichi Hiraki
发明人： Tatsuo Akiyama , Yutaka Koshino , Shunichi Hiraki
IPC分类号： H01L21/033 , H01L21/285 , H01L21/338 , H01L29/417 , H01L29/80 , H01L29/812 , H01L21/306 , B44C1/22 , C03C15/00 , C23F1/02
CPC分类号： H01L29/66871 , H01L21/033 , H01L21/28587 , H01L29/80 , H01L29/812
摘要： A method of manufacturing a GaAs FET is disclosed. In this manufacturing method, a protection film is formed on a GaAs substrate and a dummy gate electrode is formed thereon. A channel length setting film is isotropically formed on the dummy gate electrode to have a constant thickness. Then, an impurity is ion-implanted in the channel length setting film. Thereafter, the channel length setting film is removed. An etching preventive film is anisotropically formed along a substantially vertical direction with respect to the GaAs substrate. The dummy gate electrode is etched using the etching preventive film as a mask so as to form a first opening in the etching preventive film. Then, a second opening is formed in the region of the protection film corresponding to the region in which the dummy gate electrode was present. A gate electrode is formed to be in contact with the GaAs substrate through the first and second openings.
摘要翻译：公开了一种制造GaAs FET的方法。在该制造方法中，在GaAs衬底上形成保护膜，在其上形成虚拟栅电极。通道长度设定膜在虚拟栅电极上各向同性地形成，以具有恒定的厚度。然后，在沟道长度设定膜中离子注入杂质。此后，去除通道长度设定膜。蚀刻防止膜相对于GaAs衬底沿大致垂直方向各向异性地形成。使用防蚀膜作为掩模蚀刻伪栅电极，以在防蚀膜中形成第一开口。然后，在保护膜的与存在虚拟栅电极的区域相对应的区域中形成第二开口。栅电极通过第一和第二开口形成为与GaAs衬底接触。

7. 发明授权

US4710794A Composite semiconductor device 失效
标题翻译：复合半导体器件
公开(公告)号：US4710794A
公开(公告)日：1987-12-01
申请号：US828536
申请日：1986-02-12
申请人： Yutaka Koshino , Tatsuo Akiyama , Yoshiro Baba
发明人： Yutaka Koshino , Tatsuo Akiyama , Yoshiro Baba
IPC分类号： H01L29/06 , H01L21/18 , H01L21/762 , H01L21/764 , H01L21/8222 , H01L21/8249 , H01L27/07 , H01L27/082 , H01L27/12 , H01L25/04
CPC分类号： H01L21/8249 , H01L21/187 , H01L21/76264 , H01L21/76297 , H01L21/764 , H01L21/8222 , H01L27/0716 , H01L27/0825 , H01L21/76286 , H01L21/76289
摘要： Disclosed is a composite semiconductor device, comprising a composite substrate consisting of first and second semiconductor substrates, one surface of each of which is mirror-polished, so that the mirror-polished surfaces are bonded together. The first semiconductor substrate has a space adjacent to the bonding interface, and an annular groove which communicates with the space from a surface of the first semiconductor substrate opposite the bonding interface, the annular groove being formed in a portion of the first semiconductor substrate corresponding to a peripheral edge portion of the space thereof, at least one pillar projecting through the space to the bonding interface from a surface, which is exposed to the space, of a first portion of the first semiconductor substrate which is defined by the space and the annular groove, a first insulating layer, formed in the annular groove, for electrically isolating the first portion from a second portion of the first semiconductor substrate adjacent thereto, a second insulating layer, formed on the pillar or a bonding interface between the pillar and the second semiconductor substrate, for electrically isolating the first portion from the second semiconductor substrate, a first functional element formed in the first portion, and a second functional element formed in the second portion.
摘要翻译：公开了一种复合半导体器件，其包括由第一和第二半导体衬底组成的复合衬底，每个半导体衬底的一个表面被镜面抛光，使得镜面抛光表面被接合在一起。所述第一半导体衬底具有与所述接合界面相邻的空间，以及与所述第一半导体衬底的与所述接合界面相对的表面与所述空间连通的环形槽，所述环形槽形成在所述第一半导体衬底的对应于其空间的外围边缘部分，至少一个从所述空间向所述接合界面突出的第一半导体衬底的第一部分暴露于所述空间的表面的至少一个柱，所述第一部分由所述空间和环形槽，形成在环形槽中的第一绝缘层，用于将第一部分与与其相邻的第一半导体衬底的第二部分电隔离;形成在柱上的第二绝缘层或柱与第二绝缘层之间的接合界面半导体衬底，用于将第一部分与第二半导体衬底电隔离，第一形成在第一部分中的功能元件和形成在第二部分中的第二功能元件。

8. 发明授权

US5637894A Solid state image sensor device with single-layered transfer electrodes 失效
标题翻译：具有单层转移电极的固态图像传感器装置
公开(公告)号：US5637894A
公开(公告)日：1997-06-10
申请号：US544834
申请日：1995-10-18
申请人： Masako Hori , Masaaki Ogawa , Hidenori Shibata , Yoshiyuki Shioyama , Yutaka Koshino
发明人： Masako Hori , Masaaki Ogawa , Hidenori Shibata , Yoshiyuki Shioyama , Yutaka Koshino
IPC分类号： G09F9/00 , H01L21/339 , H01L27/148 , H01L29/762
CPC分类号： H01L27/14831
摘要： A charge coupled device, together with a method for manufacturing the device, is provided which can eliminate a conventional problem, that is, the remaining of a light-receiving film at a great step area and a consequent lowering of a sensitivity resulting from the shutting-off of a portion of incident light. In the charge coupled device, insulating areas are formed in substantially strip-like array on a silicon substrate. Respective transfer electrodes are formed on a gate insulating film on a semiconductor substrate with an insulating areas interposed. The respective phase transfer electrodes are electrically separated by the insulating area. By doing so, the respective phase transfer electrodes can be formed on the same plane without leaving a greater step. This can achieve a thinned light shielding film.
摘要翻译：提供了电荷耦合器件，以及用于制造器件的方法，其可以消除常规问题，即，在大步进区域处的光接收膜的剩余部分以及由此导致的灵敏度的降低一部分入射光。在电荷耦合器件中，绝缘区域在硅衬底上形成为大致带状的阵列。各个传输电极形成在半导体衬底上的绝缘膜上的绝缘膜上。各个相转移电极被绝缘区域电隔离。通过这样做，各个相转移电极可以形成在同一平面上，而不会留下更大的台阶。这可以实现减薄的遮光膜。

9. 发明授权

US4968932A Evaluation method for semiconductor device 失效
标题翻译：半导体器件的评估方法
公开(公告)号：US4968932A
公开(公告)日：1990-11-06
申请号：US251601
申请日：1988-09-30
申请人： Yoshiro Baba , Yutaka Koshino , Seiji Yasuda
发明人： Yoshiro Baba , Yutaka Koshino , Seiji Yasuda
IPC分类号： G01R19/00 , G01R31/26 , G01R31/265 , G01R31/311 , H01L21/66
CPC分类号： G01R31/2656 , G01R31/2608 , G01R31/311
摘要： An evaluation method for a semiconductor device includes the steps of applying a reverse bias voltage between an N-type substrate formed in a surface of the semiconductor device and a P-type region formed in a surface of the N-type substrate to form a depletion layer along the junction therebetween, scanning the surface of the semiconductor device is one direction with a light beam to cause an optical beam induced current to be flow across the junction, and measuring the OBIC intensity profile on a scanning line extending across the depletion layer in the surfaces of the N-type substrate and P-type region. In the method, the light beam has a wavelength whose penetration length is smaller than the depth or thickness of the P-type region, the OBIC intensity profile is integrated over a range corresponding to the depletion layer, and the integrated value is normalized by the reverse bias voltage to determine the surface potential distribution of the semiconductor device.

10. 发明授权

US4566174A Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US4566174A
公开(公告)日：1986-01-28
申请号：US545545
申请日：1983-10-26
申请人： Seiji Yasuda , Yutaka Koshino , Toshio Yonezawa
发明人： Seiji Yasuda , Yutaka Koshino , Toshio Yonezawa
IPC分类号： H01L27/082 , H01L21/20 , H01L21/74 , H01L21/761 , H01L21/8224 , H01L21/8228 , H01L21/8238 , H01L21/76
CPC分类号： H01L21/74 , H01L21/8224 , H01L21/82285 , H01L21/8238 , H01L27/0826 , Y10S148/05
摘要： A method of manufacturing a semiconductor device wherein a pair of grooves having different depths are formed in a surface of a semiconductor substrate, an epitaxial layer of one conductivity type is grown to a depth enough to fill a shallower one of the grooves, and an epitaxial layer of the opposite conductivity type is further grown to a depth enough to fill a deeper one of the grooves, followed by the step of etching the entire surface to expose the surface of said semiconductor substrate and to leave in each groove an epitaxial layer of mutually different conductivity type and having the same depth and width. A semiconductor device as manufactured by the above method.
摘要翻译：一种制造半导体器件的方法，其中在半导体衬底的表面中形成具有不同深度的一对沟槽，一个导电类型的外延层生长到足以填充较浅的一个沟槽的深度，并且外延相反导电类型的层进一步生长到足以填充更深的一个沟槽的深度，接着是蚀刻整个表面以暴露所述半导体衬底的表面并且在每个沟槽中留下相互的外延层的步骤不同的导电类型，具有相同的深度和宽度。通过上述方法制造的半导体器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式