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1. 发明授权

US5119371A Automotive multipath transmission system with power always supplied to at least two transmission unit 失效
标题翻译：电力供应至少两台变电站的汽车多路传输系统
公开(公告)号：US5119371A
公开(公告)日：1992-06-02
申请号：US423988
申请日：1989-10-18
申请人： Kiyoshi Inoue , Atsuhiko Suzuki , Yukio Nanpo , Yusaku Himono , Osamu Michihira , Yuichi Ito
发明人： Kiyoshi Inoue , Atsuhiko Suzuki , Yukio Nanpo , Yusaku Himono , Osamu Michihira , Yuichi Ito
IPC分类号： H04L25/02 , B60R16/02 , B60R16/03 , H04L12/40 , H04Q9/06
CPC分类号： B60R16/0315 , H04L12/10 , H04L12/40006 , B60R2016/0322 , H04L2012/40273 , Y02B60/33
摘要： A multipath transmission system for an automobile according to the present invention comprises a plurality of multiplex transmission units connected in parallel with each other to one common bus. Each transmission unit is assigned to one of groups in which various devices attached to the automobile are classified. The transmission unit includes a sending circuit for transmitting the multiple signals from the devices in the group concerned to the other units through the bus. The system further comprises a power source for always applying electric power to the sending circuit of at least one of the multiplex transmission units. Only that multiplex transmission unit to which the electric power is always applied is provided with a bias circuit which sets the potential of the multiple signals on the bus when the multiple signals are supplied from the sending circuits of any multiplex transmission unit to the bus.

2. 发明授权

US4951281A Multiplex transmission system 失效
公开(公告)号：US4951281A
公开(公告)日：1990-08-21
申请号：US277060
申请日：1988-11-28
申请人： Makoto Muto , Kyosuke Hasimoto , Yutaka Matsuda , Yusaku Himono , Kiyoshi Inoue , Teruhisa Inoue , Osamu Michihira , Yuichi Ito
发明人： Makoto Muto , Kyosuke Hasimoto , Yutaka Matsuda , Yusaku Himono , Kiyoshi Inoue , Teruhisa Inoue , Osamu Michihira , Yuichi Ito
IPC分类号： H04L29/14 , H04L1/00 , H04L1/16 , H04L1/18 , H04L12/413
CPC分类号： H04L1/1803 , H04L1/1614 , H04L1/1657 , H04L1/1692 , H04L12/413 , H04L2001/0094 , H04L2012/40273
摘要： A multiplex transmission system, in which a node as a transmission node transmits data frame by frame to a transmission path, and a plurality of other nodes, as reception nodes, returns a reception acknowledgment signal to the transmission path upon proper reception of the frame of data. Each of the reception nodes which properly received the frame returns the reception acknowledgment signal specific thereto to that division of a reception acknowledgment signal area in the frame which corresponds to this node. Each node discriminates the success/failure of signal transmission, by comparing the information registered beforehand in its reception acknowledgment signal table with the information in the reception acknowledgment signal area. When the information of the reception acknowledgment signal table does not coincide with that of the reception acknowledgment signal area, the transmission node re-transmits the frame and the reception acknowledgment signal tables of all the nodes are updated. The system can not only effect the addition and deletion of multiplex nodes easily without requiring the change of scale of the circuit of the system, but also discriminate trouble for each of the multiplex nodes.

3. 发明授权

US4914654A Multiplex transmission system 失效
标题翻译：多路传输系统
公开(公告)号：US4914654A
公开(公告)日：1990-04-03
申请号：US177497
申请日：1988-04-04
申请人： Yutaka Matsuda , Teruhisa Inoue , Kyousuke Hashimoto , Kiyoshi Inoue , Yusaku Himono
发明人： Yutaka Matsuda , Teruhisa Inoue , Kyousuke Hashimoto , Kiyoshi Inoue , Yusaku Himono
IPC分类号： H04L1/00 , H04L1/16 , H04L12/413
CPC分类号： H04L1/1664 , H04L1/0083 , H04L12/4135 , H04L2001/0094 , H04L2012/40273
摘要： A multiplex transmission system, in which one of a plurality of nodes, as a transmission node, mutually coupled together through a transmission path transmits data frame by frame to at least one of other nodes as at least one of reception node, and the reception node returns a reception acknowledge signal to the transmitting node upon proper reception of the frame of data. A reception acknowledge signal area comprising a plurality of bits is provided following the frame transmitted from the transmitting node. The reception acknowledge signal area is divided into a plurality of bit areas which are respectively assigned to the plurality of nodes. The reception node returns the reception acknowlege signal to the transmitting node from the respectively-assigned bit areas of the reception acknowledge signal area. As desired, a destination designation area having the same length as the reception acknowledge signal area is provided in a frame and is divided into a plurality of bit areas which are respectively assigned with the plurality of nodes. The individual destination nodes are specified by the respective bit areas of the destination designation area of the frame. Preferably, a pulse width modulation code for discriminating the binary logic based on the size of the pulse width is used as a transmission code at least in the reception acknowledge signal area.

4. 发明授权

US5307340A Multipath transmission system with a troubleshooting arrangement for detecting failure 失效
标题翻译：多路传输系统，具有检测故障的故障排除
公开(公告)号：US5307340A
公开(公告)日：1994-04-26
申请号：US815922
申请日：1991-12-30
申请人： Kiyoshi Inoue , Kyosuke Hashimoto , Yutaka Matsuda , Shoji Hara , Kunio Odaka , Seiji Hirano , Osamu Michihira , Yoshikazu Nobutoki
发明人： Kiyoshi Inoue , Kyosuke Hashimoto , Yutaka Matsuda , Shoji Hara , Kunio Odaka , Seiji Hirano , Osamu Michihira , Yoshikazu Nobutoki
IPC分类号： B60R16/02 , B60R16/03 , H04L12/413 , H04J3/14
CPC分类号： H04L12/40182 , H04L12/4135 , B60R16/0315
摘要： A multipath transmission system according to the present invention comprises a plurality of multiplex nodes connected to two multiplex buses. Each of the multiplex nodes is assigned to a specific apparatus, and includes a communication control circuit (LSI) for fetching multiplex signals from the apparatus and transmitting the multiplex signals to the multiplex buses. One multiplex node, out of the plurality of multiplex nodes, includes communication control circuits driver/receiver circuits, and troubleshooting driver/receiver circuits, which are connected to the multiplex buses and used for signal transfer between the buses, and a microprocessor for troubleshooting the multiplex buses and the multiplex nodes. The multiplex node relays a failure signal, corresponding to the result of troubleshooting, to the other network which suffers no trouble.
摘要翻译：根据本发明的多径传输系统包括连接到两个多路复用总线的多个复用节点。每个多路复用节点被分配给特定装置，并且包括用于从装置取出多路复用信号并将多路复用信号发送到多路复用总线的通信控制电路（LSI）。在多个多路复用节点中的一个多路复用节点包括连接到多路复用总线并用于总线之间的信号传输的通信控制电路驱动器/接收器电路和故障排除驱动器/接收器电路以及用于故障排除的微处理器多路复用总线和多路复用节点。多路复用节点将与故障诊断结果相对应的故障信号中继到没有故障的其他网络。

5. 发明授权

US5357525A Multiplex transmission system 失效
标题翻译：多路传输系统
公开(公告)号：US5357525A
公开(公告)日：1994-10-18
申请号：US860897
申请日：1992-03-31
申请人： Hiroo Moriue , Yutaka Matsuda , Kyosuke Hashimoto , Kiyoshi Inoue , Seiji Hirano , Osamu Michihira , Yoshikazu Nobutoki , Hiroaki Sakamoto
发明人： Hiroo Moriue , Yutaka Matsuda , Kyosuke Hashimoto , Kiyoshi Inoue , Seiji Hirano , Osamu Michihira , Yoshikazu Nobutoki , Hiroaki Sakamoto
IPC分类号： H04L1/00 , H04L1/18 , H04L25/49 , G08C25/02
CPC分类号： H04L1/1874 , H04L1/1803 , H04L25/4902 , H04L2001/0093
摘要： A multiplex transmission system of this invention includes a plurality of multiplex nodes interconnected by a common multiplex transmission line. A frame of data is transmitted among the multiplex nodes through the multiplex transmission line. When a data frame transmitted from an air conditioner switch multiplex node (subnode) is received, an air conditioner unit multiplex node (main node), which is predetermined as a destination node, detects the contents of each data from an ID-a of the received data, performs a calculation on SOM to DATA 4 received, generates collation data (CRC) in accordance with the result of the calculation and transmits same. The subnode generates collation data (CRC), which is an error check code, through a calculation on the transmitted SOM to DATA 4, and compares the thus-generated CRC with the CRC received from the main node, to determine whether or not the data transmission was properly carried out. When the data transmission was carried out properly, the subnode returns a signal ACK3, and when the data transmission failed, the data frame is retransmitted, whereby the subnode need not have an ACK management function.
摘要翻译：本发明的复用传输系统包括通过公共多路复用传输线互连的多个复用节点。通过复用传输线在多路复用节点之间传输数据帧。当接收到从空调开关多路复用节点（子节点）发送的数据帧时，作为目的地节点预先确定的空调机组复用节点（主节点）从ID-a的每个数据的内容检测出接收到的数据，对接收到的数据4进行SOM计算，根据计算结果生成核对数据（CRC）并进行发送。子节点通过对发送的SOM到DATA 4的计算产生作为错误校验码的校验数据（CRC），并将这样生成的CRC与从主节点接收到的CRC进行比较，以确定数据是否传输得到了适当的实施。当数据传输正确进行时，子节点返回信号ACK3，当数据传输失败时，数据帧被重传，子节点不需要具有ACK管理功能。

6. 发明授权

US5321689A Multipath transmission system 失效
标题翻译：多路传输系统
公开(公告)号：US5321689A
公开(公告)日：1994-06-14
申请号：US24815
申请日：1993-03-01
申请人： Atsuhiko Suzuki , Kiyoshi Inoue , Kyosuke Hashimoto
发明人： Atsuhiko Suzuki , Kiyoshi Inoue , Kyosuke Hashimoto
IPC分类号： H04L25/49 , H04L9/14 , H04L12/413 , H04J3/14
CPC分类号： H04L12/40182 , H04L12/40013 , H04L12/4135 , H04L25/14 , H04L2012/40215
摘要： A multipath transmission system of this invention includes a plurality of multiplex nodes connected in parallel to three common signal transmission lines. The multiplex node includes a transmission control circuit which is allotted to a corresponding one of devices, receives a multiplex signal from the device in response to a transmission request of another multiplex node and transmits the multiplex signal to the signal transmission line. It includes a voltage detection circuit for detecting a voltage generated in at least one of the transmission lines, a reception control circuit for specifying the transmission state of the signal transmission line according to a voltage detected by the voltage detection circuit, a communication control device for communicating with the multiplex nodes to detect fault, and a voltage setting circuit for changing a voltage of the signal transmission line when fault is detected by the communication control device.
摘要翻译：本发明的多径传输系统包括与三个公共信号传输线并联连接的多个复用节点。多路复用节点包括分配给相应设备的传输控制电路，响应于另一个多路复用节点的传输请求从设备接收多路复用信号，并将该多路复用信号发送到信号传输线路。它包括用于检测在至少一个传输线中产生的电压的电压检测电路，用于根据由电压检测电路检测的电压指定信号传输线的传输状态的接收控制电路，用于与多路复用节点通信以检测故障;以及电压设置电路，用于在由通信控制设备检测到故障时改变信号传输线路的电压。

7. 发明授权

US09535383B2 Image forming apparatus 有权
标题翻译：图像形成装置
公开(公告)号：US09535383B2
公开(公告)日：2017-01-03
申请号：US13087482
申请日：2011-04-15
申请人： Kiyoshi Inoue
发明人： Kiyoshi Inoue
IPC分类号： G03G15/36 , H04N1/00 , H04N1/38 , H04N1/387 , G03G15/00
CPC分类号： B41J13/0009 , G03G15/36 , G03G15/50 , G03G15/502 , G03G2215/00569 , G03G2215/00582 , G06F3/1218 , G06F3/1219 , H04N1/00002 , H04N1/00015 , H04N1/00031 , H04N1/00053 , H04N1/00063 , H04N1/3873 , H04N2201/0094
摘要： When trial printing is executed in a repeat printing mode, trial printing is performed in size of an image of one piece in a layout in which a plurality of images are supposed to be printed in the repeat printing mode normally. A user who has checked a finished state of the trial printing sets, when the finished state is in a desired state, the recording paper on which the trial printing is performed to the paper feed portion again and executes the repeat printing. Thereby, in a blank space excluding a print image which is printed with a first time trial printing, a scheduled quantity of a plurality of images are repeatedly printed.
摘要翻译：当在重复打印模式下执行试打印时，在重复打印模式中正常地应该以多张图像被打印的布局中的一个图像的大小执行试打印。当完成状态处于期望状态时，已经检查了试纸打印的完成状态的用户再次对进纸部分进行了试纸打印的记录纸，并执行了重复打印。由此，除了在第一次试打印上打印的打印图像之外的空白空间中，重复打印多张图像的调度量。

8. 发明申请

US20120127792A1 SEMICONDUCTOR MEMORY HAVING ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELLS 有权
标题翻译：具有电可擦除和可编程半导体存储器单元的半导体存储器
公开(公告)号：US20120127792A1
公开(公告)日：2012-05-24
申请号：US13363400
申请日：2012-02-01
申请人： Kunihiro KATAYAMA , Takayuki Tamura , Kiyoshi Inoue
发明人： Kunihiro KATAYAMA , Takayuki Tamura , Kiyoshi Inoue
IPC分类号： G11C16/10
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： In a nonvolatile memory apparatus, a system bus receives address, command, and/or control signals. Memory cells store bits of data by shifting a threshold voltage to one of plural ranges. In writing a first page, the threshold voltage of a first memory cell remains in a first range or shifts into a second range. In writing a second page, the threshold voltage remains in the first or second voltages, or shifts into a third range from the first range or into a fourth range from the second range. Before writing the second page, the memory reads data from the first memory cell for generating the second page writing data. A shifting direction of the threshold voltage from the first to the second range is the same as a shifting direction from the first to the third range.
摘要翻译：在非易失性存储装置中，系统总线接收地址，命令和/或控制信号。存储单元通过将阈值电压移位到多个范围之一来存储数据位。在写入第一页时，第一存储器单元的阈值电压保持在第一范围或者移位到第二范围。在写第二页时，阈值电压保持在第一或第二电压中，或者从第二范围移动到从第一范围到第四范围的第三范围。在写入第二页之前，存储器从第一存储器单元读取用于生成第二页写入数据的数据。从第一到第二范围的阈值电压的移动方向与从第一到第三范围的移动方向相同。

9. 发明申请

US20110122701A1 SEMICONDUCTOR MEMORY HAVING ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELLS 有权
公开(公告)号：US20110122701A1
公开(公告)日：2011-05-26
申请号：US13019048
申请日：2011-02-01
申请人： Kunihiro KATAYAMA , Takayuki Tamura , Kiyoshi Inoue
发明人： Kunihiro KATAYAMA , Takayuki Tamura , Kiyoshi Inoue
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

10. 发明授权

US07881111B2 Semiconductor memory having electrically erasable and programmable semiconductor memory cells 有权
标题翻译：具有电可擦除和可编程的半导体存储器单元的半导体存储器
公开(公告)号：US07881111B2
公开(公告)日：2011-02-01
申请号：US12504307
申请日：2009-07-16
申请人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
发明人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.
摘要翻译：一种可电气可变的非易失性多级存储器件和操作这种器件的方法，其包括将至少一个存储器单元的状态设置为从包括至少第一至第四电平状态的多个状态中选择的一种状态响应于要存储在一个存储器单元中的信息，并且通过利用在第二和第二电平状态之间设置的第一参考电平来读取存储单元的状态来确定读出状态是否对应于第一至第四电平状态之一第三电平状态，在第一和第二电平状态之间设置的第二参考电平和在第三和第四电平状态之间设置的第三参考电平。

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