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1. 发明授权

US07226839B1 Method and system for improving the topography of a memory array 有权
标题翻译：用于改善存储器阵列的形貌的方法和系统
公开(公告)号：US07226839B1
公开(公告)日：2007-06-05
申请号：US10861575
申请日：2004-06-04
申请人： King Wai Kelwin Ko , Hiroyuki Kinoshita , Hiroyuki Ogawa , Yu Sun
发明人： King Wai Kelwin Ko , Hiroyuki Kinoshita , Hiroyuki Ogawa , Yu Sun
IPC分类号： H01L21/8234
CPC分类号： H01L27/105 , H01L21/76819 , H01L21/76838 , H01L21/7684 , H01L27/115 , H01L27/11521 , H01L27/11526 , Y10S438/926
摘要： A method and system for improving the topography of a memory array is disclosed. In one embodiment, a dummy bitline is formed over a field oxide region at an interface between a memory array and interface circuitry. In addition, a poly-2 layer is applied above the dummy bitline on the field oxide region wherein the utilization of the field oxide region for placement of the dummy bitline provides a uniform surface between an actual bitline and the periphery of the memory array. Furthermore, a landing pad is formed at the end of the dummy bitline on the field oxide region, wherein the dummy bitline does not cause erroneous operation of the landing pad.
摘要翻译：公开了一种用于改善存储器阵列的形貌的方法和系统。在一个实施例中，在存储器阵列和接口电路之间的接口处的场氧化物区域上形成虚拟位线。此外，在场氧化物区域上的虚拟位线之上施加多晶硅层2，其中用于放置虚拟位线的场氧化物区域的利用在实际位线和存储器阵列的外围之间提供均匀的表面。此外，在场氧化物区域上的虚拟位线的末端形成着陆焊盘，其中虚拟位线不会引起着陆焊盘的错误操作。

2. 发明授权

US07301193B2 Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell 有权
标题翻译：浮动栅极存储单元中低Vss电阻和减少DIBL的结构和方法
公开(公告)号：US07301193B2
公开(公告)日：2007-11-27
申请号：US10762445
申请日：2004-01-22
申请人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
发明人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
摘要翻译：根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

3. 发明申请

US20050164450A1 Structure and method for low Vss resistance and reduced dibl in a floating gate memory cell 有权
标题翻译：浮动栅极存储单元的低Vss电阻和二极管的结构和方法
公开(公告)号：US20050164450A1
公开(公告)日：2005-07-28
申请号：US10762445
申请日：2004-01-22
申请人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
发明人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L21/28 , H01L21/336 , H01L21/74 , H01L29/417 , H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
摘要翻译：根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

4. 发明授权

US06808992B1 Method and system for tailoring core and periphery cells in a nonvolatile memory 有权
标题翻译：用于定制非易失性存储器中的核心和外围单元的方法和系统
公开(公告)号：US06808992B1
公开(公告)日：2004-10-26
申请号：US10150240
申请日：2002-05-15
申请人： Kelwin Ko , Shenqing Fang , Angela T. Hui , Hiroyuki Kinoshita , Wenmei Li , Yu Sun , Hiroyuki Ogawa
发明人： Kelwin Ko , Shenqing Fang , Angela T. Hui , Hiroyuki Kinoshita , Wenmei Li , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536 , H01L29/6656
摘要： A method and system for providing a semiconductor device are described. The semiconductor device includes a substrate, a core and a periphery. The core includes a plurality of core gate stacks having a first plurality of edges, while the periphery a plurality of periphery gate stacks having a second plurality of edges. The method and system include providing a plurality of core spacers, a plurality of periphery spacers, a plurality of core sources and a plurality of conductive regions. The core spacers reside at the first plurality of edges and have a thickness. The periphery spacers reside at the second plurality of edges and have a second thickness greater than the first thickness. The core sources reside between the plurality of core gate stacks. The conductive regions are on the plurality of core sources. This method allows different thicknesses of the spacers to be formed in the core and the periphery so that the spacers can be tailored to the different requirements of the core and periphery.
摘要翻译：描述了一种用于提供半导体器件的方法和系统。半导体器件包括衬底，芯和周边。芯包括具有第一多个边缘的多个核心栅极叠层，而周边具有多个具有第二多个边缘的外围栅极堆叠。该方法和系统包括提供多个芯间隔件，多个外围间隔件，多个芯源和多个导电区域。芯间隔件位于第一多个边缘处并且具有厚度。外围间隔件位于第二多个边缘处并且具有大于第一厚度的第二厚度。核心源位于多个核心门堆栈之间。导电区域在多个核心源上。该方法允许不同厚度的间隔件形成在芯部和周边中，使得间隔件可以根据芯部和周边的不同要求进行调整。

5. 发明授权

US06974995B1 Method and system for forming dual gate structures in a nonvolatile memory using a protective layer 失效
标题翻译：使用保护层在非易失性存储器中形成双栅极结构的方法和系统
公开(公告)号：US06974995B1
公开(公告)日：2005-12-13
申请号：US10032757
申请日：2001-12-27
申请人： Angela Hui , Shenqing Fang , Hiroyuki Kinoshita , Kelwin Ko , Wenmei Li , Yu Sun , Hiroyuki Ogawa , Chi Chang
发明人： Angela Hui , Shenqing Fang , Hiroyuki Kinoshita , Kelwin Ko , Wenmei Li , Yu Sun , Hiroyuki Ogawa , Chi Chang
IPC分类号： H01L21/8238 , H01L21/8239 , H01L27/105 , H01L29/772
CPC分类号： H01L21/823842 , H01L27/1052
摘要： A method and system for providing a semiconductor device is described. The semiconductor includes a core and a periphery. The method and system include providing a plurality of core gate stacks in the core, a plurality of sources in the core and a plurality of periphery gate stacks in the periphery. Each of the plurality of core gate stacks includes a first polysilicon gate and a WSi layer above the first polysilicon gate. The plurality of sources resides between a portion of the plurality of core gate stacks. Each of the plurality of periphery gate stacks includes a second polysilicon gate and a CoSi layer on the second polysilicon gate.
摘要翻译：描述了一种用于提供半导体器件的方法和系统。半导体包括芯和外围。所述方法和系统包括在芯中提供多个核心堆栈，在核心中提供多个源极和在周边的多个外围栅极叠层。多个核心栅堆叠中的每一个包括第一多晶硅栅极和位于第一多晶硅栅极上方的WSi层。多个源位于多个核心栅极叠层的一部分之间。多个外围栅极堆叠中的每一个在第二多晶硅栅极上包括第二多晶硅栅极和CoSi层。

6. 发明授权

US08564042B2 Dual storage node memory 有权
标题翻译：双存储节点存储器
公开(公告)号：US08564042B2
公开(公告)日：2013-10-22
申请号：US11702845
申请日：2007-02-05
申请人： Fred Cheung , Hiroyuki Kinoshita , Chungho Lee , Yu Sun , Chi Chang
发明人： Fred Cheung , Hiroyuki Kinoshita , Chungho Lee , Yu Sun , Chi Chang
IPC分类号： H01L29/94
CPC分类号： H01L29/66833 , G11C16/0475 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521
摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and second charge storage elements. The insulating layer provides insulation between the first and second charge storage elements.
摘要翻译：本发明的实施例涉及存储单元。存储单元包括第一电荷存储元件和第二电荷存储元件，其中第一和第二电荷存储元件包括氮化物。存储单元还包括形成在第一和第二电荷存储元件之间的绝缘层。绝缘层提供第一和第二电荷存储元件之间的绝缘。

7. 发明申请

US20070117303A1 Semiconductor memory device (as amended) 有权
标题翻译：半导体存储器件（经修改）
公开(公告)号：US20070117303A1
公开(公告)日：2007-05-24
申请号：US11656438
申请日：2007-01-23
申请人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
发明人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468 , H01L27/115 , H01L27/11568 , Y10S257/90
摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).
摘要翻译：漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并掺杂杂质的重掺杂深杂质区域（7b）其浓度高于轻掺杂浅杂质区（7a）的浓度。轻掺杂的浅杂质区（7a）导致短沟道效应和编程效率的提高。漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

8. 发明授权

US07060564B1 Memory device and method of simultaneous fabrication of core and periphery of same 有权
标题翻译：同时制造芯片和周边的记忆装置和方法
公开(公告)号：US07060564B1
公开(公告)日：2006-06-13
申请号：US10635089
申请日：2003-08-06
申请人： Inkuk Kang , Hiroyuki Kinoshita , Weidong Qian , Kelwin King Wai Ko , Yu Sun
发明人： Inkuk Kang , Hiroyuki Kinoshita , Weidong Qian , Kelwin King Wai Ko , Yu Sun
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A method of fabricating a memory device having a core region of double-bit memory cells and a periphery region of logic circuitry includes forming a dielectric stack over the core and periphery areas of a semiconductor substrate and removing the dielectric stack from the periphery region. A gate dielectric is formed over the periphery area, followed by a first conductive layer over the core and periphery areas. After the formation and thermal processing of the gate dielectric, bitlines, which serve as source and drain regions, are implanted into the core area. Formation of the bitlines after the gate dielectric layer reduces lateral bitline diffusion and reduces short channel effects.
摘要翻译：一种制造具有双位存储器单元的核心区域和逻辑电路的外围区域的存储器件的方法包括在半导体衬底的芯部和外围区域上形成电介质堆叠并从外围区域去除电介质堆叠。在外围区域上形成栅极电介质，随后在芯部和外围区域上形成第一导电层。在栅极电介质的形成和热处理之后，用作源极和漏极区的位线被植入核心区域。栅介质层之后的位线形成减少了横向位线扩散并减少了短沟道效应。

9. 发明授权

US06780708B1 METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY 有权
标题翻译：形成核心和外围门的方法，包括两个关键掩蔽步骤，以形成一个核心区域的硬掩模，其中包括在一个分辨率限制下无法达到的关键尺寸
公开(公告)号：US06780708B1
公开(公告)日：2004-08-24
申请号：US10382744
申请日：2003-03-05
申请人： Hiroyuki Kinoshita , Yu Sun , Basab Banerjee , Christopher M. Foster , John R. Behnke , Cyrus Tabery
发明人： Hiroyuki Kinoshita , Yu Sun , Basab Banerjee , Christopher M. Foster , John R. Behnke , Cyrus Tabery
IPC分类号： H01L218242
CPC分类号： H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.
摘要翻译：一种用于形成半导体器件的方法，其包括在衬底上的层中具有可变节距和临界尺寸的线和间隔图案。衬底包括第一区域（例如芯区域）和第二区域（例如，周边区域）。第一区域中的第一子线和空间图案包括尺寸（A）的空间小于单独通过光刻工艺可实现的尺寸。此外，第二区域中的第二子线和空间图案包括至少一条线，其包括通过光刻可实现的第二临界尺寸（B）。该方法使用两个关键的掩模步骤来形成硬掩模，其在芯部区域中包括小于在光刻的分辨率极限下可实现的临界尺寸（A）。此外，该方法使用单个蚀刻步骤将硬掩模的图案转移到该层。

10. 发明授权

US07759745B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07759745B2
公开(公告)日：2010-07-20
申请号：US11656437
申请日：2007-01-23
申请人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
发明人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/10 , H01L29/739
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468 , H01L27/115 , H01L27/11568 , Y10S257/90
摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).
摘要翻译：漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并在其上掺杂有杂质的重掺杂深杂质区域（7b）浓度高于轻掺杂浅杂质区（7a）的浓度。轻掺杂的浅杂质区（7a）导致短沟道效应和编程效率的改善。漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

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