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1. 发明授权

US06194115B1 Toner composition for developing electrostatic latent image 有权
标题翻译：用于显影静电潜像的调色剂组合物
公开(公告)号：US06194115B1
公开(公告)日：2001-02-27
申请号：US09369481
申请日：1999-08-05
申请人： Kimikazu Nagase , Masaaki Ishiyama , Takashi Taira , Hiroyuki Takahata , Kousuke Yotsuduka , Shigehiro Hano , Yoshihiro Chujo
发明人： Kimikazu Nagase , Masaaki Ishiyama , Takashi Taira , Hiroyuki Takahata , Kousuke Yotsuduka , Shigehiro Hano , Yoshihiro Chujo
IPC分类号： G03G9097
CPC分类号： G03G9/08 , G03G9/097 , G03G9/09733 , G03G15/201
摘要： The invention in this application relates to a toner composition for electrostatic latent image development which is characterized in that, in a toner composition comprising at least binder resin, colorant and charge control agent, to be used in a print forming method provided with a print fixing device which fixes the toner image on a recording medium by means of a light flash, the concentration of benzene generated by heating for 90 seconds at 330° C. is no more than 60 &mgr;g/g, and the invention provides a toner composition for electrostatic latent image development which either extends the filter life or does not require the use of a filter.
摘要翻译：本发明涉及用于静电潜像显影的调色剂组合物，其特征在于，在至少包含粘合剂树脂，着色剂和电荷控制剂的调色剂组合物中，用于具有印刷定影通过闪光将调色剂图像固定在记录介质上的装置，通过在330℃下加热90秒产生的苯浓度不超过60mug / g，本发明提供了一种用于静电的调色剂组合物可以延长过滤器使用寿命或不需要使用过滤器的潜像显影。

2. 发明授权

US5521037A Intermediate transfer material, and an image forming method using it 失效
标题翻译：中间转印材料，以及使用它的成像方法
公开(公告)号：US5521037A
公开(公告)日：1996-05-28
申请号：US307787
申请日：1994-11-30
申请人： Kimikazu Nagase , Takashi Taira , Sachio Suzuki , Hisayoshi Yamada
发明人： Kimikazu Nagase , Takashi Taira , Sachio Suzuki , Hisayoshi Yamada
IPC分类号： G03G7/00 , G03G15/16 , G03G13/16
CPC分类号： G03G7/0046 , G03G15/162 , G03G7/0053 , G03G7/008
摘要： The present invention relates to an intermediate transfer material, used for an image forming method of developing an electrostatic latent image on an electrostatic latent image carrier utilizing a liquid toner, electrostatically transferring the image visualized by development onto an intermediate transfer material, and re-transferring visible image from the intermediate transfer material onto final transfer objects, utilizing as the intermediate transfer material at least a silicone rubber layer, an adhesive layer and a conductive fluorine rubber layer in this order from the outer surface side thereof.The intermediate transfer material of the present invention is excellent in durability and transferability, and so the image forming method using said intermediate transfer material can provide a high quality image at high reproducibility.
摘要翻译： PCT No.PCT / JP94 / 00125 Sec。 371日期1994年11月30日 102（e）1994年11月30日日期PCT 1994年1月28日PCT PCT。公开号WO94 / 18608 日期：1994年8月18日。本发明涉及一种中间转印材料，其用于使用液体调色剂在静电潜像载体上显影静电潜像的图像形成方法，将通过显影可视化的图像静电转印到中间体转印材料，并将可见图像从中间转印材料再转印到最终转印体上，从其外表面侧依次使用至少一种硅橡胶层，粘合剂层和导电氟橡胶层作为中间转印材料。本发明的中间转印材料的耐久性和转印性优异，因此使用所述中间转印材料的图像形成方法可以以高再现性提供高质量的图像。

3. 发明授权

US6081468A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US6081468A
公开(公告)日：2000-06-27
申请号：US353856
申请日：1999-07-15
申请人： Takashi Taira , Kimimasa Imai
发明人： Takashi Taira , Kimimasa Imai
IPC分类号： G11C11/409 , G11C7/12 , G11C11/401 , G11C11/407 , G11C11/4074 , G11C11/4094 , G11C7/00 , G11C8/00
CPC分类号： G11C11/4074 , G11C11/4094 , G11C7/12
摘要： To suppress the power-on current flowing when power is tuned on in the circuit which feeds precharging current to the bit lines of the banks in a synchronous DRAM comprising a multi-bank structure. The device comprises a plurality of bank circuits BKi which are all of the same structure, wherein the bit line precharging power supply lines which the respective bank circuits have are connected in common, a first precharging power supply circuit which has its output node connected to the precharging power supply line and starts its precharging current feed operation when the power supply in the DRAM chip is turned on, and a second precharging power supply circuit which has its output node connected to the precharging power supply line and starts its precharging current feed operation after the bit line has been raised to a predetermined potential by the precharging current of the first precharging power supply circuit.
摘要翻译：为了抑制在包括多存储体结构的同步DRAM中将预充电电流馈送到存储体的位线的电路中调谐电源时的通电电流。该装置包括具有相同结构的多个组电路BKi，其中各个组电路具有共同连接的位线预充电电源线，其输出节点连接到第一预充电电源电路当DRAM芯片的电源接通时，预充电电源线开始其预充电电流馈送操作;以及第二预充电电源电路，其输出节点连接到预充电电源线，并在其之后开始其预充电电流馈电操作通过第一预充电电源电路的预充电电流将位线提高到预定电位。

4. 发明授权

US07079432B2 Semiconductor storage device formed to optimize test technique and redundancy technology 失效
标题翻译：形成半导体存储设备，以优化测试技术和冗余技术
公开(公告)号：US07079432B2
公开(公告)日：2006-07-18
申请号：US11040851
申请日：2005-01-20
申请人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe , Munehiro Yoshida
发明人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe , Munehiro Yoshida
IPC分类号： G11C7/00
CPC分类号： G11C29/785 , G11C29/26 , G11C29/787 , G11C2029/2602
摘要： A semiconductor storage device has a function of simultaneously activating a plurality of word lines connected to the same bit line via cell transistors. The semiconductor storage device comprises a column redundancy system that sets repair regions of column redundancy based on row addresses. By the column redundancy system, the repair regions are set to cause the plurality of word lines which can be activated together to belong to the same repair region, when the repair regions are set to divide the bit line.
摘要翻译：半导体存储装置具有通过单元晶体管同时激活连接到同一位线的多个字线的功能。半导体存储装置包括基于行地址设置列冗余的修复区域的列冗余系统。通过列冗余系统，当修复区域被设置为分割位线时，修复区域被设置为使得可以一起被激活的多个字线属于同一修复区域。

5. 发明授权

US07027335B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07027335B2
公开(公告)日：2006-04-11
申请号：US10720980
申请日：2003-11-24
申请人： Mikihiko Ito , Masaru Koyanagi , Takashi Taira
发明人： Mikihiko Ito , Masaru Koyanagi , Takashi Taira
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C11/4091 , G11C2207/005 , G11C2207/065 , G11C2207/2281
摘要： A semiconductor storage device comprises a memory cell array including memory cells, and bit lines for transfer of data in the memory cells; an amplifier circuit connected to the bit lines to amplify data in the memory cells; a first switching element connected between the bit lines and the amplifier circuit; a first reference voltage source which applies to the gate of the first switching element a voltage for turning the first switching element ON; a second switching element and a third switching element connected in series between the gate of the first switching element and the first reference voltage source, said second switching element and said third switching element being connected in parallel to each other; a second reference voltage source which applies to the gates of the second and third switching elements a voltage for turning the second and third switching elements ON; and a first timing shift circuit connected between the gate of the third switching element and the second reference voltage source to delay the operation of the third switching element from the operation of the second switching element.
摘要翻译：半导体存储装置包括存储单元阵列，其包括存储单元，以及用于在存储单元中传送数据的位线; 连接到位线的放大器电路，以放大存储器单元中的数据; 连接在位线与放大电路之间的第一开关元件; 第一参考电压源，其向第一开关元件的栅极施加用于使第一开关元件导通的电压; 第二开关元件和第三开关元件串联连接在第一开关元件的栅极和第一参考电压源之间，所述第二开关元件和所述第三开关元件彼此并联连接; 第二参考电压源，其向第二和第三开关元件的栅极施加用于使第二和第三开关元件接通的电压; 以及连接在第三开关元件的栅极和第二参考电压源之间的第一定时偏移电路，用于延迟第三开关元件的操作与第二开关元件的操作。

6. 发明授权

US06876588B2 Semiconductor storage device formed to optimize test technique and redundancy technology 失效
公开(公告)号：US06876588B2
公开(公告)日：2005-04-05
申请号：US10664464
申请日：2003-09-17
申请人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe , Munehiro Yoshida
发明人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe , Munehiro Yoshida
IPC分类号： G11C8/02 , G11C29/00 , G11C29/26 , G11C7/00
CPC分类号： G11C29/785 , G11C29/26 , G11C29/787 , G11C2029/2602
摘要： There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.

7. 发明申请

US20090051020A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：US20090051020A1
公开(公告)日：2009-02-26
申请号：US12035813
申请日：2008-02-22
申请人： Takashi Taira , Masaru Koyanagi
发明人： Takashi Taira , Masaru Koyanagi
IPC分类号： H01L21/58 , H01L23/495
CPC分类号： H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/49 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/30107 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor memory device includes: A method of manufacturing a semiconductor device, wherein a semiconductor chip is mounted on a lead frame including a plurality of lead lines, and terminals included in the semiconductor chip are connected to the lead lines, thereby to manufacture the semiconductor device, comprising the steps of: arranging distal end parts of the plurality of lead lines at equal intervals along a direction of a first axis, the distal end parts being connected with the terminals included in the semiconductor chip; arranging terminal parts for inputting/outputting signals, at equal intervals along a direction of a second axis; shaping intermediate parts for connecting the distal end parts and the terminal parts, so as to be bent between the distal end parts and the terminal parts; forming a half number of the plurality of lead lines and the remaining half number of the plurality of lead lines so as to have a shape of line symmetry with respect to the second axis; and mounting the semiconductor chip on a front surface side of a package.
摘要翻译：半导体存储器件包括：半导体器件的制造方法，其中将半导体芯片安装在包括多根引线的引线框架上，并且包含在半导体芯片中的端子连接到引线，从而制造半导体装置，包括以下步骤：沿着第一轴线的方向以相等的间隔布置多条引线的远端部分，所述远端部分与包括在所述半导体芯片中的端子连接; 沿着第二轴的方向以等间隔布置用于输入/输出信号的端子部分; 成形用于连接远端部分和端子部分的中间部分，以在远端部分和端部部分之间弯曲; 形成所述多根引线的半数和所述多根引线的剩余的半数，使其相对于所述第二轴具有线对称的形状; 以及将半导体芯片安装在封装的前表面侧。

8. 发明申请

US20050122802A1 Semiconductor storage device formed to optimize test technique and redundancy technology 失效
标题翻译：形成半导体存储设备，以优化测试技术和冗余技术
公开(公告)号：US20050122802A1
公开(公告)日：2005-06-09
申请号：US11040851
申请日：2005-01-20
申请人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe , Munehiro Yoshida
发明人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe , Munehiro Yoshida
IPC分类号： G11C8/02 , G11C29/00 , G11C29/26 , G11C7/00
CPC分类号： G11C29/785 , G11C29/26 , G11C29/787 , G11C2029/2602
摘要： There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.
摘要翻译：提供了一种半导体存储装置，其中只有一个缺陷元件被行冗余元件代替，以便在存储单元阵列中的多个元件是多个元件中的多个元件中的至少一个元件是有缺陷的情况下补偿缺陷同时激活。半导体存储装置包括阵列控制电路，其被配置为通过基于信号来防止接收到字线状态信号来中断故障元件的操作，以确定是否执行行冗余替换处理。字线状态信号通过单个信号线输入到单元阵列单元中的多个存储块。

9. 发明授权

US06741509B2 Semiconductor storage device formed to optimize test technique and redundancy technology 失效
标题翻译：形成半导体存储设备，以优化测试技术和冗余技术
公开(公告)号：US06741509B2
公开(公告)日：2004-05-25
申请号：US10053524
申请日：2002-01-16
申请人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe
发明人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe
IPC分类号： G11C700
CPC分类号： G11C29/785 , G11C29/26 , G11C29/787 , G11C2029/2602
摘要： There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.
摘要翻译：提供了一种半导体存储装置，其中只有一个缺陷元件被行冗余元件代替，以便在存储单元阵列中的多个元件是多个元件中的多个元件中的至少一个元件是有缺陷的情况下补偿缺陷同时激活。半导体存储装置包括阵列控制电路，其被配置为通过基于信号来防止接收到字线状态信号来中断故障元件的操作，以确定是否执行行冗余替换处理。字线状态信号通过单个信号线输入到单元阵列单元中的多个存储块。

10. 发明授权

US5831421A Semiconductor device with supply voltage-lowering circuit 失效
标题翻译：具有电源降压电路的半导体器件
公开(公告)号：US5831421A
公开(公告)日：1998-11-03
申请号：US837461
申请日：1997-04-18
申请人： Takashi Taira , Kazuyoshi Muraoka
发明人： Takashi Taira , Kazuyoshi Muraoka
IPC分类号： H01L27/04 , G05F1/46 , G11C5/14 , G11C11/401 , G11C11/407 , H01L21/822 , G05F3/16
CPC分类号： G05F1/465
摘要： A semiconductor device includes an internal circuit and first and second supply voltage-lowering circuits in its semiconductor chip. The first supply voltage-lowering circuit steps down an external power supply potential of the semiconductor chip in response to a control signal, generates a first internal power supply potential, and supplies it to the internal circuit. The second supply voltage-lowering circuit steps down the external power supply potential of the semiconductor chip in response to the control signal, generates a second internal power supply potential of substantially the same level as that of the first internal power supply potential, and supplies it to the internal circuit. The first and second internal power supply potentials output from the first and second supply voltage-lowering circuits vary out of phase with each other to cancel out variations in first and second internal power supply potentials.
摘要翻译：半导体器件包括其半导体芯片中的内部电路和第一和第二电源降压电路。第一电源降压电路响应于控制信号降低半导体芯片的外部电源电位，产生第一内部电源电位，并将其提供给内部电路。第二电源降压电路响应于控制信号降低半导体芯片的外部电源电位，产生与第一内部电源电位基本相同的第二内部电源电位，并将其提供到内部电路。从第一和第二电源电压降低电路输出的第一和第二内部电源电位彼此不同相异，以抵消第一和第二内部电源电位的变化。

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