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1. 发明申请

US20120034474A1 JOINED PRODUCT 审中-公开
标题翻译：加工产品
公开(公告)号：US20120034474A1
公开(公告)日：2012-02-09
申请号：US13264681
申请日：2010-05-26
申请人： Kimihiro Ozaki , Keizo Kobayashi , Hideki Moriguchi , Tomoyuki Ishida , Akihiko Ikegaya , Tomohiro Fukaya , Takashi Hirao , Takeru Nakashima , Mitsuo Nishimura , Akio Fujimura
发明人： Kimihiro Ozaki , Keizo Kobayashi , Hideki Moriguchi , Tomoyuki Ishida , Akihiko Ikegaya , Tomohiro Fukaya , Takashi Hirao , Takeru Nakashima , Mitsuo Nishimura , Akio Fujimura
IPC分类号： B32B15/04 , B32B19/00
CPC分类号： B23K31/025 , B23B27/18 , B23B2226/125 , B23B2226/315 , B23B2240/00 , B23K1/0008 , B23K1/19 , B23K20/008 , B23K20/023 , B23K20/16 , B23K20/22 , B23K35/325 , B23K35/327 , B23K2101/20 , B23K2101/34 , B23K2103/18 , B23K2103/52 , Y10T428/31678
摘要： A joined product according to the present invention is a joined product including a cemented carbide sintered compact serving as a first material to be joined and a cBN sintered compact or a diamond sintered compact serving as a second material to be joined. The first material to be joined and the second material to be joined are joined by a joining material that forms a liquid phase at a temperature exceeding 800° C. and lower than 1000° C. and that is placed between the first material to be joined and the second material to be joined. The first material to be joined and the second material to be joined are joined by resistance heating and pressing at a pressure of 0.1 to 200 MPa.
摘要翻译：根据本发明的接合产品是包括用作第一接合材料的硬质合金烧结体和作为第二接合材料的cBN烧结体或金刚石烧结体的接合体。要接合的第一材料和待接合的第二材料通过在超过800℃且低于1000℃的温度下形成液相的接合材料接合，并且被放置在待接合的第一材料之间和第二待接合材料。第一待接合材料和第二待接合材料通过电阻加热和压力为0.1〜200MPa的条件进行接合。

2. 发明申请

US20130246716A1 MEMORY SYSTEM AND DATA WRITING METHOD 有权
标题翻译：记忆系统和数据写入方法
公开(公告)号：US20130246716A1
公开(公告)日：2013-09-19
申请号：US13616466
申请日：2012-09-14
申请人： Ryoichi KATO , Mitsunori Tadokoro , Takashi Hirao
发明人： Ryoichi KATO , Mitsunori Tadokoro , Takashi Hirao
IPC分类号： G06F3/06
CPC分类号： G06F3/064 , G06F3/0616 , G06F3/0679 , G06F12/0246 , G06F2212/7203 , G06F2212/7205
摘要： According to one embodiment, when a controller writes update data in a second memory to a first memory which is nonvolatile and a difference between a size of a page and a size of the update data is equal to or greater than a size of a cluster, the controller configured to generate write data by adding, to the update data, data which has the size of the cluster, store an update content of management information corresponding to the update data and an update content storage position indicating a storage position of the update content of the management information in the first memory, and write the generated write data to a block in writing of the first memory.
摘要翻译：根据一个实施例，当控制器将第二存储器中的更新数据写入非易失性的第一存储器，并且页面的大小与更新数据的大小之间的差等于或大于集群的大小时，所述控制器被配置为通过向所述更新数据添加具有所述集群的大小的数据来存储与所述更新数据相对应的管理信息的更新内容和指示所述更新内容的存储位置的更新内容存储位置来生成写入数据的第一存储器中的管理信息，并将生成的写入数据写入到第一存储器的写入块中。

3. 发明授权

US08125206B2 Semiconductor device and power supply using the same 有权
标题翻译：半导体器件和电源使用相同
公开(公告)号：US08125206B2
公开(公告)日：2012-02-28
申请号：US12143305
申请日：2008-06-20
申请人： Noboru Akiyama , Takayuki Hashimoto , Takashi Hirao , Koji Tateno
发明人： Noboru Akiyama , Takayuki Hashimoto , Takashi Hirao , Koji Tateno
IPC分类号： G05F1/40
CPC分类号： H02M3/1588 , Y02B70/1466
摘要： A power-supply control IC is included in a switching power supply which drives to turn on and off a semiconductor switching device connected to a DC power supply in series to supply a predetermined constant voltage to an external load, and is a semiconductor device including a semiconductor circuit which controls on and off of the semiconductor switching device. When a current flowing through the load is abruptly increased to cause an error voltage to exceed a predetermined first threshold voltage after the end of a PWM on-pulse generated in synchronization with a switching cycle, a second PWM on-pulse is generated within the same switching cycle. Furthermore, in a plurality of switching cycles after the switching cycle in which the second PWM on-pulse is generated, the first threshold voltage for comparison with the error voltage is switched to a second threshold voltage higher than the first threshold voltage.
摘要翻译：电源控制IC包括在开关电源中，该开关电源驱动以串联连接到直流电源的半导体开关装置，以向外部负载提供预定的恒定电压，并且是包括控制半导体开关器件的导通和截止的半导体电路。当流过负载的电流突然增加以在与开关周期同步产生的PWM导通脉冲结束之后导致误差电压超过预定的第一阈值电压时，在同一时间内产生第二PWM导通脉冲开关周期。此外，在产生第二PWM导通脉冲的开关周期之后的多个开关周期中，与误差电压进行比较的第一阈值电压被切换到高于第一阈值电压的第二阈值电压。

4. 发明授权

US07928505B2 Semiconductor device with vertical trench and lightly doped region 失效
标题翻译：具有垂直沟槽和轻掺杂区域的半导体器件
公开(公告)号：US07928505B2
公开(公告)日：2011-04-19
申请号：US12326392
申请日：2008-12-02
申请人： Takashi Hirao , Takayuki Hashimoto , Noboru Akiyama
发明人： Takashi Hirao , Takayuki Hashimoto , Noboru Akiyama
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： The vertical trench MOSFET comprises: an N type epitaxial region formed on an upper surface of an N+ type substrate having a drain electrode on a lower surface thereof; a gate trench extending from a front surface into the N type epitaxial region; a gate electrode positioned in the gate trench so as to interpose an insulator; a channel region formed on the N type epitaxial region; a source region formed on the channel region; a source electrode formed on the source region; a source trench extending from the front surface into the N type epitaxial region; and a trench-buried source electrode positioned in the source trench so as to interpose an insulator, wherein the source electrode contacts with the trench-buried source electrode.
摘要翻译：垂直沟槽MOSFET包括：形成在其下表面上具有漏电极的N +型衬底的上表面上的N型外延区域; 栅极沟槽，其从前表面延伸到N型外延区域; 位于所述栅极沟槽中以便插入绝缘体的栅电极; 形成在N型外延区上的沟道区; 形成在沟道区上的源极区; 形成在源极区上的源电极; 源极沟槽，其从前表面延伸到N型外延区域; 以及位于所述源极沟槽中以便插入绝缘体的沟槽埋入式源电极，其中所述源电极与所述沟槽埋入式源极接触。

5. 发明申请

US20090015224A1 DC-DC CONVERTER, DRIVER IC, AND SYSTEM IN PACKAGE 有权
标题翻译： DC-DC转换器，驱动器IC和封装中的系统
公开(公告)号：US20090015224A1
公开(公告)日：2009-01-15
申请号：US12171347
申请日：2008-07-11
申请人： Takashi Hirao , Takayuki Hashimoto , Masaki Shiraishi
发明人： Takashi Hirao , Takayuki Hashimoto , Masaki Shiraishi
IPC分类号： H02M3/156
CPC分类号： H02M3/158 , H01L2224/05554 , H01L2224/0603 , H01L2224/48137 , H01L2224/48195 , H01L2224/49175 , H01L2924/12032 , H01L2924/1305 , H01L2924/13091 , H01L2924/30107 , H03K17/162 , H03K17/6871 , H03K19/018521 , H03K2217/0081 , H01L2924/00
摘要： A DC-DC converter that prevents self turn-on and improves the power efficiency is provided. In a non-insulated DC-DC converter, self turn-on is prevented by applying a negative voltage between a gate and a source of a low side MOSFET by the use of a capacitor for generating negative voltage when the low side MOSFET is in an OFF state. Also, when the low side MOSFET is in an ON state due to the capacitor for generating negative voltage, a positive voltage applied between the gate and the source of the low side MOSFET does not drop from a voltage of a gate driving DC power source that is supplied from a gate power input terminal. Therefore, the power efficiency is improved.
摘要翻译：提供了防止自身接通并提高功率效率的DC-DC转换器。在非绝缘DC-DC转换器中，通过在低侧MOSFET处于低压MOSFET的栅极和源极之间通过使用用于产生负电压的电容器施加负电压来防止自身接通 OFF状态。此外，由于用于产生负电压的电容器，当低端MOSFET处于导通状态时，施加在低侧MOSFET的栅极和源极之间的正电压不会从栅极驱动DC电源的电压下降，由栅极电源输入端子提供。因此，功率效率得到提高。

6. 发明申请

US20070187678A1 Semiconductor device including active layer made of zinc oxide with controlled orientations and manufacturing method thereof 有权
标题翻译：包括由受控取向的氧化锌制成的活性层的半导体装置及其制造方法
公开(公告)号：US20070187678A1
公开(公告)日：2007-08-16
申请号：US11704838
申请日：2007-02-09
申请人： Takashi Hirao , Mamoru Furuta , Hiroshi Furuta , Tokiyoshi Matsuda , Takahiro Hiramatsu
发明人： Takashi Hirao , Mamoru Furuta , Hiroshi Furuta , Tokiyoshi Matsuda , Takahiro Hiramatsu
IPC分类号： H01L29/10
CPC分类号： H01L21/02422 , H01L21/02491 , H01L21/02494 , H01L21/02554 , H01L21/02595 , H01L21/02609 , H01L21/02631 , H01L29/04 , H01L29/045 , H01L29/4908 , H01L29/7869 , H01L29/78693
摘要： A semiconductor device includes an oxide semiconductor thin film layer primarily including zinc oxide having at least one orientation other than (002) orientation. The zinc oxide may have a mixed orientation including (002) orientation and (101) orientation. Alternatively, the zinc oxide may have a mixed orientation including (100) orientation and (101) orientation.
摘要翻译：半导体器件包括氧化物半导体薄膜层，其主要包括具有除（002）取向之外的至少一个取向的氧化锌。氧化锌可以具有包括（002）取向和（101）取向的混合取向。或者，氧化锌可以具有包括（100）取向和（101）取向的混合取向。

7. 发明授权

US6105225A Method of manufacturing a thin film sensor element 失效
标题翻译：制造薄膜传感器元件的方法
公开(公告)号：US6105225A
公开(公告)日：2000-08-22
申请号：US600863
申请日：1996-02-09
申请人： Hideo Torii , Takeshi Kamada , Shigenori Hayashi , Ryoichi Takayama , Takashi Hirao , Masumi Hattori
发明人： Hideo Torii , Takeshi Kamada , Shigenori Hayashi , Ryoichi Takayama , Takashi Hirao , Masumi Hattori
IPC分类号： G01P15/08 , G01P15/09 , H01L41/29 , H01L41/22
CPC分类号： G01P15/0922 , G01P15/0802 , H01L41/0478 , H01L41/0815 , H01L41/313 , Y10T29/42 , Y10T29/4981
摘要： A method of manufacturing a small, light, highly accurate and inexpensive thin film sensor element is disclosed. The thin film sensor element comprises a sensor holding substrate having an opening part and a multilayer film structure adhered thereon. The multilayer film structure comprises a first electrode film, a second electrode film, and a piezoelectric dielectric oxide film present between the first and second electrode films. The method of manufacturing the thin film sensor element comprises the steps of: forming the multilayer film structure by forming the first electrode film having a (100) plane orientation on a surface of an alkali halide substrate, forming the piezoelectric dielectric oxide thereon, and forming the second electrode film on the piezoelectric dielectric oxide; adhering the multilayer film structure on the surface of the sensor holding substrate having the opening part; and dissolving and removing the alkali halide substrate with water.
摘要翻译：公开了一种制造小型，轻型，高精度和廉价的薄膜传感器元件的方法。薄膜传感器元件包括具有开口部分和粘附在其上的多层膜结构的传感器保持基板。多层膜结构包括第一电极膜，第二电极膜和存在于第一和第二电极膜之间的压电电介质氧化物膜。制造薄膜传感器元件的方法包括以下步骤：通过在碱金属卤化物衬底的表面上形成具有（100）面取向的第一电极膜来形成多层膜结构，在其上形成压电电介质氧化物，并形成压电电介质氧化物上的第二电极膜; 将多层膜结构粘附在具有开口部的传感器保持基板的表面上; 并用水溶解和除去碱金属卤化物基质。

8. 发明授权

US4861729A Method of doping impurities into sidewall of trench by use of plasma source 失效
标题翻译：通过使用等离子体源将杂质掺杂到沟槽的侧壁中的方法
公开(公告)号：US4861729A
公开(公告)日：1989-08-29
申请号：US088216
申请日：1987-08-24
申请人： Genshu Fuse , Takashi Hirao , Takashi Ohzone
发明人： Genshu Fuse , Takashi Hirao , Takashi Ohzone
IPC分类号： H01L21/223
CPC分类号： H01L21/2236
摘要： A method in which in order to dope impurities, with excellent controllability, into a sidewall of a trench formed in a semiconductor substrate, plasma is generated in a gas including the impurities and the semiconductor substrate is disposed in or near the plasma, so that the impurities may be doped into the sidewall of the trench uniformly and at high precision of concentration control; wherein one of a duluted B.sub.2 H.sub.6 gas and diluted AsH.sub.3 gas is chosen as the gas of the plasma, whereby one of B and As as the impurities directly enters the sidewall of the trench without first passing through a film.
摘要翻译：为了将具有优异的可控性的杂质掺杂到在半导体衬底中形成的沟槽的侧壁中的方法中，在包括杂质的气体中产生等离子体，并且半导体衬底设置在等离子体中或其附近，使得杂质可以均匀地并且以高精度的浓度控制被掺杂到沟槽的侧壁中; 其中选择一个掺杂的B2H6气体和稀释的AsH3气体作为等离子体的气体，由此作为杂质的B和As中的一个直接进入沟槽的侧壁，而不首先通过膜。

9. 发明授权

US4800174A Method for producing an amorphous silicon semiconductor device using a multichamber PECVD apparatus 失效
标题翻译：使用多室PECVD装置制造非晶硅半导体器件的方法
公开(公告)号：US4800174A
公开(公告)日：1989-01-24
申请号：US50699
申请日：1987-05-18
申请人： Shinichiro Ishihara , Masatoshi Kitagawa , Takashi Hirao
发明人： Shinichiro Ishihara , Masatoshi Kitagawa , Takashi Hirao
IPC分类号： H01L21/205 , C23C16/24 , C23C16/54 , H01L31/04
CPC分类号： C23C16/54 , C23C16/24 , Y10S148/025 , Y10S148/045 , Y10S148/072 , Y10S438/908
摘要： A method of producing an amorphous silicon semiconductor device makes use of a capacitance-coupled high-frequency glow-discharge semiconductor production apparatus which is equipped with a plurality of glow-discharge chambers each having a high-frequency electrode and a substrate holder opposing each other and means for supplying material gases to the glow-discharge chambers. A reaction of a material gas is effected in a first glow-discharge chamber, so as to form a semiconductor layer having a first conductivity type on a substrate introduced into the first glow-discharge chamber, and, after moving the substrate into a second glow-discharge chamber, a reaction of a material gas different from the material gas used in the first glow-discharge chamber is effected, thereby forming a semiconductor layer having a second conductivity type on the semiconductor layer of the first conductivity type. The substrate with the semiconductor layer of the first conductivity formed thereon is moved from the first glow-discharge chamber to the second glow-discharge chamber after a predetermined gas atmosphere is formed in the first glow-discharge chamber. The distance between the electrode and the substrate holder is made smaller in one of the first and second glow-discharge chambers which is designed for forming the thicker one of the semiconductor layers of the first and second conductivity types than in the other of the first and second glow-discharge chambers. The temperature of the substrate is set higher in one of the first and second glow-discharge chambers which is designed for forming the thicker one of the semiconductor layers of the first and second conductivity types than in the other of the first and second glow-discharge chambers.
摘要翻译：一种非晶硅半导体器件的制造方法采用电容耦合高频辉光放电半导体制造装置，该装置配备有多个辉光放电室，每个辉光放电室具有彼此相对的高频电极和衬底保持器以及用于将材料气体供应到辉光放电室的装置。在第一辉光放电室中进行材料气体的反应，以便在引入第一辉光放电室的衬底上形成具有第一导电类型的半导体层，并且在将衬底移动到第二发光进行与第一辉光放电室中使用的材料气体不同的原料气体的反应，由此在第一导电型半导体层上形成具有第二导电类型的半导体层。在第一辉光放电室中形成规定的气体气氛之后，将形成有第一导电性的半导体层的基板从第一辉光放电室向第二辉光放电室移动。在第一和第二辉光放电室之一中，电极和衬底保持器之间的距离较小，被设计用于形成第一和第二导电类型的较厚的一个半导体层，而不是第一和第二导电类型中的另一个，第二个辉光放电室。第一和第二辉光放电室之一的衬底的温度被设定为高于在第一和第二辉光放电中的另一个中形成第一和第二导电类型的较厚的一个半导体层的第一和第二辉光放电室房间。

10. 发明授权

US09251055B2 Memory system and control method of memory system 有权
标题翻译：内存系统和内存系统的控制方法
公开(公告)号：US09251055B2
公开(公告)日：2016-02-02
申请号：US13599087
申请日：2012-08-30
申请人： Shinji Yonezawa , Takashi Hirao , Hirokuni Yano , Mitsunori Tadokoro , Hiroki Matsudaira , Akira Sawaoka
发明人： Shinji Yonezawa , Takashi Hirao , Hirokuni Yano , Mitsunori Tadokoro , Hiroki Matsudaira , Akira Sawaoka
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7205 , G06F2212/7209 , G11C2211/5641
摘要： A memory system in embodiments includes a nonvolatile semiconductor memory that stores user data, a forward lookup address translation table and a reverse lookup address translation table, and a controller. The controller is configured to determine that the user data stored in the nonvolatile semiconductor memory is valid or invalid based on these two tables. The controller may perform data organizing of selecting data determined valid and rewriting the data in a new block. The controller may perform write processing and rewriting processing to the new block alternately at a predetermined ratio. The controller may determine whether a predetermined condition is satisfied on a basis of addresses included in write requests and write data in the MLC mode when the condition is satisfied and write data in the SLC mode when the condition is not satisfied.
摘要翻译：实施例中的存储器系统包括存储用户数据的非易失性半导体存储器，正向查找地址转换表和反向查找地址转换表以及控制器。控制器被配置为基于这两个表来确定存储在非易失性半导体存储器中的用户数据有效或无效。控制器可以执行数据组织，选择确定有效的数据并在新的块中重写数据。控制器可以以预定的比例交替地对新的块执行写入处理和重写处理。当条件满足时，控制器可以基于写入请求中包括的地址和写入数据来确定是否满足预定条件，并且当条件不满足时将控制器写入SLC模式中的数据。

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