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1. 发明申请

US20090080129A1 Semiconductor chips having improved electrostatic discharge protection circuit arrangement 有权
标题翻译：具有改善的静电放电保护电路布置的半导体芯片
公开(公告)号：US20090080129A1
公开(公告)日：2009-03-26
申请号：US12292026
申请日：2008-11-10
申请人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
发明人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
IPC分类号： H02H9/00 , H01L23/62
CPC分类号： H01L23/60 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.
摘要翻译：半导体芯片可以包括布置在至少第一和第二行中的多个焊盘以及连接到多个焊盘的多个保护电路。多个保护电路可以包括至少一个二极管。第一保护电路可以连接到第一排焊盘中的第一焊盘，并且第二保护电路可以连接到第二排焊盘中的第二焊盘。第一和第二保护电路可以布置在第一排焊盘的下方。

2. 发明授权

US07898034B2 Semiconductor chips having improved electrostatic discharge protection circuit arrangement 有权
标题翻译：具有改善的静电放电保护电路布置的半导体芯片
公开(公告)号：US07898034B2
公开(公告)日：2011-03-01
申请号：US12292026
申请日：2008-11-10
申请人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
发明人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
IPC分类号： H01L23/62
CPC分类号： H01L23/60 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.
摘要翻译：半导体芯片可以包括布置在至少第一和第二行中的多个焊盘以及连接到多个焊盘的多个保护电路。多个保护电路可以包括至少一个二极管。第一保护电路可以连接到第一排焊盘中的第一焊盘，并且第二保护电路可以连接到第二排焊盘中的第二焊盘。第一和第二保护电路可以布置在第一排焊盘的下方。

3. 发明申请

US20070176241A1 Semiconductor chips having improved electrostatic discharge protection circuit arrangement 有权
标题翻译：具有改善的静电放电保护电路布置的半导体芯片
公开(公告)号：US20070176241A1
公开(公告)日：2007-08-02
申请号：US11654638
申请日：2007-01-18
申请人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
发明人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
IPC分类号： H01L23/62
CPC分类号： H01L23/60 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.
摘要翻译：半导体芯片可以包括布置在至少第一和第二行中的多个焊盘以及连接到多个焊盘的多个保护电路。多个保护电路可以包括至少一个二极管。第一保护电路可以连接到第一排焊盘中的第一焊盘，并且第二保护电路可以连接到第二排焊盘中的第二焊盘。第一和第二保护电路可以布置在第一排焊盘的下方。

4. 发明授权

US07465993B2 Semiconductor chips having improved electrostatic discharge protection circuit arrangement 有权
标题翻译：具有改善的静电放电保护电路布置的半导体芯片
公开(公告)号：US07465993B2
公开(公告)日：2008-12-16
申请号：US11654638
申请日：2007-01-18
申请人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
发明人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
IPC分类号： H01L23/62
CPC分类号： H01L23/60 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.
摘要翻译：半导体芯片可以包括布置在至少第一和第二行中的多个焊盘以及连接到多个焊盘的多个保护电路。多个保护电路可以包括至少一个二极管。第一保护电路可以连接到第一排焊盘中的第一焊盘，并且第二保护电路可以连接到第二排焊盘中的第二焊盘。第一和第二保护电路可以布置在第一排焊盘的下方。

5. 发明申请

US20160163690A1 ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND ELECTRONIC DEVICE HAVING THE SAME 有权
标题翻译：静电放电保护装置和具有该静电放电保护装置的电子装置
公开(公告)号：US20160163690A1
公开(公告)日：2016-06-09
申请号：US14809299
申请日：2015-07-27
申请人： Jae-Hyok Ko , Han-Gu Kim , Han-Gu Kim , Jong-Kyu Song , Jin Heo
发明人： Jae-Hyok Ko , Han-Gu Kim , Han-Gu Kim , Jong-Kyu Song , Jin Heo
IPC分类号： H01L27/02 , H01L29/06 , H01L29/36 , H01L29/10
CPC分类号： H01L27/0262 , H01L27/027
摘要： In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.
摘要翻译：在ESD保护装置中，第一导电类型的第一阱和第二导电类型的第二阱形成在基板中以彼此接触。第一导电类型的第一杂质区和第二导电类型的第二杂质区形成在第一阱中，并且电连接到第一电极焊盘。第二杂质区域在第二阱的方向上与第一杂质区间隔开。在第二阱中形成第三杂质区，具有第二导电类型，并且电连接到第二电极焊盘。在第二阱中形成第四杂质区，位于第一阱的从第三杂质区方向接触第三杂质区，具有第一导电类型，并且是电漂浮的。

6. 发明申请

US20070177329A1 Voltage clamping circuits using MOS transistors and semiconductor chips having the same and methods of clamping voltages 有权
标题翻译：使用具有相同的MOS晶体管和半导体芯片的钳位电路以及钳位电压的方法
公开(公告)号：US20070177329A1
公开(公告)日：2007-08-02
申请号：US11646535
申请日：2006-12-28
申请人： Kyoung-Sik Im , Han-Gu Kim , Jae-Hyok Ko , Il-Hun Son , Suk-Jin Kim
发明人： Kyoung-Sik Im , Han-Gu Kim , Jae-Hyok Ko , Il-Hun Son , Suk-Jin Kim
IPC分类号： H05F3/02
CPC分类号： H05K9/0067
摘要： A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.
摘要翻译：提供了钳位电路，其可以通过使用已经包括在电路中的晶体管将电路节点处的电压钳位到稳定的电平。当发生静电放电（ESD）时，钳位电路可以将半导体芯片内的电路的第一节点处的电压钳位到更稳定的水平。钳位电路可以包括晶体管和电容元件，以存储控制电压以响应于ESD来导通晶体管。

7. 发明授权

US07697249B2 Voltage clamping circuits using MOS transistors and semiconductor chips having the same and methods of clamping voltages 有权
标题翻译：使用具有相同的MOS晶体管和半导体芯片的钳位电路以及钳位电压的方法
公开(公告)号：US07697249B2
公开(公告)日：2010-04-13
申请号：US11646535
申请日：2006-12-28
申请人： Kyoung-Sik Im , Han-Gu Kim , Jae-Hyok Ko , Il-Hun Son , Suk-Jin Kim
发明人： Kyoung-Sik Im , Han-Gu Kim , Jae-Hyok Ko , Il-Hun Son , Suk-Jin Kim
IPC分类号： H02H3/22
CPC分类号： H05K9/0067
摘要： A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.
摘要翻译：提供了钳位电路，其可以通过使用已经包括在电路中的晶体管将电路节点处的电压钳位到稳定的电平。当发生静电放电（ESD）时，钳位电路可以将半导体芯片内的电路的第一节点处的电压钳位到更稳定的水平。钳位电路可以包括晶体管和电容元件，以存储控制电压以响应于ESD来导通晶体管。

8. 发明授权

US08174806B2 Electrostatic discharge protection element and electrostatic discharge protection circuit including the same 有权
标题翻译：静电放电保护元件与静电放电保护电路相同
公开(公告)号：US08174806B2
公开(公告)日：2012-05-08
申请号：US12658700
申请日：2010-02-12
申请人： Suk-Jin Kim , Han-Gu Kim , Jae-Hyok Ko , Hyo-Cheol Ban , Min-Chang Ko , Kyoung-Ki Jeon
发明人： Suk-Jin Kim , Han-Gu Kim , Jae-Hyok Ko , Hyo-Cheol Ban , Min-Chang Ko , Kyoung-Ki Jeon
IPC分类号： H02H9/00
CPC分类号： H01L27/0676 , H01L27/0288
摘要： An electrostatic discharge (ESD) protection element includes a first diode, a second diode, and a poly resistor. The first diode is connected between a first voltage and an input/output (I/O) pad. The second diode is connected between the I/O pad and a second voltage. The poly resistor is formed on the second diode.
摘要翻译：静电放电（ESD）保护元件包括第一二极管，第二二极管和聚电阻。第一个二极管连接在第一个电压和一个输入/输出（I / O）焊盘之间。第二个二极管连接在I / O焊盘和第二个电压之间。多电阻形成在第二二极管上。

9. 发明申请

US20100214705A1 Electrostatic discharge protection element and electrostatic discharge protection circuit including the same 有权
标题翻译：静电放电保护元件与静电放电保护电路相同
公开(公告)号：US20100214705A1
公开(公告)日：2010-08-26
申请号：US12658700
申请日：2010-02-12
申请人： Suk-Jin Kim , Han-Gu Kim , Jae-Hyok Ko , Hyo-Cheol Ban , Min-Chang Ko , Kyoung-Ki Jeon
发明人： Suk-Jin Kim , Han-Gu Kim , Jae-Hyok Ko , Hyo-Cheol Ban , Min-Chang Ko , Kyoung-Ki Jeon
IPC分类号： H02H9/04 , H01L27/06
CPC分类号： H01L27/0676 , H01L27/0288
摘要： An electrostatic discharge (ESD) protection element includes a first diode, a second diode, and a poly resistor. The first diode is connected between a first voltage and an input/output (I/O) pad. The second diode is connected between the I/O pad and a second voltage. The poly resistor is formed on the second diode.
摘要翻译：静电放电（ESD）保护元件包括第一二极管，第二二极管和聚电阻。第一个二极管连接在第一个电压和一个输入/输出（I / O）焊盘之间。第二个二极管连接在I / O焊盘和第二个电压之间。多电阻形成在第二二极管上。

10. 发明授权

US09620502B2 Semiconductor device including an extended impurity region 有权
公开(公告)号：US09620502B2
公开(公告)日：2017-04-11
申请号：US14178480
申请日：2014-02-12
申请人： Chan-Hee Jeon , Eun-Kyoung Kwon , Il-Ryong Kim , Han-Gu Kim , Woo-Jin Seo , Ki-Tae Lee
发明人： Chan-Hee Jeon , Eun-Kyoung Kwon , Il-Ryong Kim , Han-Gu Kim , Woo-Jin Seo , Ki-Tae Lee
IPC分类号： H01L27/088 , H01L29/66 , H01L27/11
CPC分类号： H01L21/823814 , H01L21/02529 , H01L21/02532 , H01L21/266 , H01L21/76805 , H01L21/76895 , H01L21/823821 , H01L21/823871 , H01L23/535 , H01L27/0288 , H01L27/0886 , H01L27/0924 , H01L27/1104 , H01L27/1116 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/7848
摘要： In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.

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