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1. 发明授权

US07697249B2 Voltage clamping circuits using MOS transistors and semiconductor chips having the same and methods of clamping voltages 有权
标题翻译：使用具有相同的MOS晶体管和半导体芯片的钳位电路以及钳位电压的方法
公开(公告)号：US07697249B2
公开(公告)日：2010-04-13
申请号：US11646535
申请日：2006-12-28
申请人： Kyoung-Sik Im , Han-Gu Kim , Jae-Hyok Ko , Il-Hun Son , Suk-Jin Kim
发明人： Kyoung-Sik Im , Han-Gu Kim , Jae-Hyok Ko , Il-Hun Son , Suk-Jin Kim
IPC分类号： H02H3/22
CPC分类号： H05K9/0067
摘要： A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.
摘要翻译：提供了钳位电路，其可以通过使用已经包括在电路中的晶体管将电路节点处的电压钳位到稳定的电平。当发生静电放电（ESD）时，钳位电路可以将半导体芯片内的电路的第一节点处的电压钳位到更稳定的水平。钳位电路可以包括晶体管和电容元件，以存储控制电压以响应于ESD来导通晶体管。

2. 发明申请

US20070177329A1 Voltage clamping circuits using MOS transistors and semiconductor chips having the same and methods of clamping voltages 有权
标题翻译：使用具有相同的MOS晶体管和半导体芯片的钳位电路以及钳位电压的方法
公开(公告)号：US20070177329A1
公开(公告)日：2007-08-02
申请号：US11646535
申请日：2006-12-28
申请人： Kyoung-Sik Im , Han-Gu Kim , Jae-Hyok Ko , Il-Hun Son , Suk-Jin Kim
发明人： Kyoung-Sik Im , Han-Gu Kim , Jae-Hyok Ko , Il-Hun Son , Suk-Jin Kim
IPC分类号： H05F3/02
CPC分类号： H05K9/0067
摘要： A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.
摘要翻译：提供了钳位电路，其可以通过使用已经包括在电路中的晶体管将电路节点处的电压钳位到稳定的电平。当发生静电放电（ESD）时，钳位电路可以将半导体芯片内的电路的第一节点处的电压钳位到更稳定的水平。钳位电路可以包括晶体管和电容元件，以存储控制电压以响应于ESD来导通晶体管。

3. 发明授权

US08358490B2 Transistor with EOS protection and ESD protection circuit including the same 有权
标题翻译：具有EOS保护和ESD保护电路的晶体管包括相同
公开(公告)号：US08358490B2
公开(公告)日：2013-01-22
申请号：US12213231
申请日：2008-06-17
申请人： Chan-Hee Jeon , Kyoung-Sik Im , Hyun-Jun Choi , Han-Gu Kim
发明人： Chan-Hee Jeon , Kyoung-Sik Im , Hyun-Jun Choi , Han-Gu Kim
IPC分类号： H02H9/00 , H02H3/20 , H02H9/04
CPC分类号： H01L27/0285 , H01L29/0692 , H01L29/0847 , H01L29/4238 , H01L29/78
摘要： A transistor with an electrical overstress (EOS) protection may include an active region, a plurality of impurity regions and a conduction pattern. The active region may be formed in a substrate. The impurity regions may be formed in the active region and arranged at a predetermined or given distance with respect to each other. The conduction pattern may be arranged between each of the impurity regions in a meandering shape, and the conduction pattern may include a center portion connected to a ground terminal. Therefore, a transistor with EOS protection, a clamp device, and an ESD protection circuit including the same may increase an on-time of a clamp device and may sufficiently discharge a charge due to the EOS by including a conduction pattern configured with gates that are connected with respect to each other in a meandering shape.
摘要翻译：具有电应力（EOS）保护的晶体管可以包括有源区，多个杂质区和导电图。有源区可以形成在衬底中。杂质区域可以形成在有源区域中并相对于彼此以预定或给定的距离布置。导电图案可以以蜿蜒的形状布置在每个杂质区之间，并且导电图案可以包括连接到接地端子的中心部分。因此，具有EOS保护的晶体管，钳位装置和包括该晶体管的ESD保护电路可以增加钳位装置的导通时间，并且可以通过包括配置有栅极的导通图案来充分地放电由于EOS引起的电荷，以蜿蜒的形状相对于彼此连接。

4. 发明申请

US20080310061A1 Transistor with EOS protection and ESD protection circuit including the same 有权
标题翻译：具有EOS保护和ESD保护电路的晶体管包括相同
公开(公告)号：US20080310061A1
公开(公告)日：2008-12-18
申请号：US12213231
申请日：2008-06-17
申请人： Chan-Hee Jeon , Kyoung-Sik Im , Hyun-Jun Choi , Han-Gu Kim
发明人： Chan-Hee Jeon , Kyoung-Sik Im , Hyun-Jun Choi , Han-Gu Kim
IPC分类号： H02H9/00 , H01L29/78
CPC分类号： H01L27/0285 , H01L29/0692 , H01L29/0847 , H01L29/4238 , H01L29/78
摘要： A transistor with an electrical overstress (EOS) protection may include an active region, a plurality of impurity regions and a conduction pattern. The active region may be formed in a substrate. The impurity regions may be formed in the active region and arranged at a predetermined or given distance with respect to each other. The conduction pattern may be arranged between each of the impurity regions in a meandering shape, and the conduction pattern may include a center portion connected to a ground terminal. Therefore, a transistor with EOS protection, a clamp device, and an ESD protection circuit including the same may increase an on-time of a clamp device and may sufficiently discharge a charge due to the EOS by including a conduction pattern configured with gates that are connected with respect to each other in a meandering shape.
摘要翻译：具有电应力（EOS）保护的晶体管可以包括有源区，多个杂质区和导电图。有源区可以形成在衬底中。杂质区域可以形成在有源区域中并相对于彼此以预定或给定的距离布置。导电图案可以以蜿蜒的形状布置在每个杂质区之间，并且导电图案可以包括连接到接地端子的中心部分。因此，具有EOS保护的晶体管，钳位装置和包括该晶体管的ESD保护电路可以增加钳位装置的导通时间，并且可以通过包括配置有栅极的导电图案来充分地放电由于EOS引起的电荷，以蜿蜒的形状相对于彼此连接。

5. 发明申请

US20060258067A1 Device for protecting against electrostatic discharge 审中-公开
标题翻译：用于防止静电放电的装置
公开(公告)号：US20060258067A1
公开(公告)日：2006-11-16
申请号：US11430916
申请日：2006-05-10
申请人： Chan-Hee Jeon , Kyoung-Sik Im
发明人： Chan-Hee Jeon , Kyoung-Sik Im
IPC分类号： H01L21/84 , H01L29/74
CPC分类号： H01L29/7436 , H01L27/0262 , H01L27/0921 , H01L29/87
摘要： A device, for protecting against electrostatic discharge, structured as a PNPN junction, includes: first and second conductivity type regions formed in a substrate, contacting each other; a first diffusion layer of second conductivity type dopants formed in the first conductivity type region and electrically connected to an anode; a second diffusion layer of first conductivity type dopants formed in the second conductivity type region and electrically connected to a cathode; and at least one of (A) a third diffusion layer of first conductivity type dopants formed in the first conductivity type region between the first diffusion layer and the second conductivity type region and electrically connected to the anode through a first external resistor, and a (B) fourth diffusion layer of second conductivity type dopants formed in the second conductivity type region between the second diffusion layer and the first conductivity type region and electrically connected to the cathode through a second external resistor.
摘要翻译：用于防止静电放电的装置，其构造为PNPN结，包括：形成在基板中的第一和第二导电类型区域，彼此接触; 形成在第一导电类型区域中并电连接到阳极的第二导电类型掺杂剂的第一扩散层; 形成在第二导电类型区域中并电连接到阴极的第一导电类型掺杂剂的第二扩散层; 以及（A）第一导电型掺杂剂的第三扩散层中的至少一个，其形成在第一扩散层和第二导电类型区域之间的第一导电类型区域中，并且通过第一外部电阻器与阳极电连接， B）第二传导型掺杂剂的第四扩散层，形成在第二扩散层和第一导电类型区域之间的第二导电类型区域中，并通过第二外部电阻器电连接到阴极。

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