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1. 发明授权

US09620502B2 Semiconductor device including an extended impurity region 有权
公开(公告)号：US09620502B2
公开(公告)日：2017-04-11
申请号：US14178480
申请日：2014-02-12
申请人： Chan-Hee Jeon , Eun-Kyoung Kwon , Il-Ryong Kim , Han-Gu Kim , Woo-Jin Seo , Ki-Tae Lee
发明人： Chan-Hee Jeon , Eun-Kyoung Kwon , Il-Ryong Kim , Han-Gu Kim , Woo-Jin Seo , Ki-Tae Lee
IPC分类号： H01L27/088 , H01L29/66 , H01L27/11
CPC分类号： H01L21/823814 , H01L21/02529 , H01L21/02532 , H01L21/266 , H01L21/76805 , H01L21/76895 , H01L21/823821 , H01L21/823871 , H01L23/535 , H01L27/0288 , H01L27/0886 , H01L27/0924 , H01L27/1104 , H01L27/1116 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/7848
摘要： In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.

2. 发明申请

US20080310061A1 Transistor with EOS protection and ESD protection circuit including the same 有权
标题翻译：具有EOS保护和ESD保护电路的晶体管包括相同
公开(公告)号：US20080310061A1
公开(公告)日：2008-12-18
申请号：US12213231
申请日：2008-06-17
申请人： Chan-Hee Jeon , Kyoung-Sik Im , Hyun-Jun Choi , Han-Gu Kim
发明人： Chan-Hee Jeon , Kyoung-Sik Im , Hyun-Jun Choi , Han-Gu Kim
IPC分类号： H02H9/00 , H01L29/78
CPC分类号： H01L27/0285 , H01L29/0692 , H01L29/0847 , H01L29/4238 , H01L29/78
摘要： A transistor with an electrical overstress (EOS) protection may include an active region, a plurality of impurity regions and a conduction pattern. The active region may be formed in a substrate. The impurity regions may be formed in the active region and arranged at a predetermined or given distance with respect to each other. The conduction pattern may be arranged between each of the impurity regions in a meandering shape, and the conduction pattern may include a center portion connected to a ground terminal. Therefore, a transistor with EOS protection, a clamp device, and an ESD protection circuit including the same may increase an on-time of a clamp device and may sufficiently discharge a charge due to the EOS by including a conduction pattern configured with gates that are connected with respect to each other in a meandering shape.
摘要翻译：具有电应力（EOS）保护的晶体管可以包括有源区，多个杂质区和导电图。有源区可以形成在衬底中。杂质区域可以形成在有源区域中并相对于彼此以预定或给定的距离布置。导电图案可以以蜿蜒的形状布置在每个杂质区之间，并且导电图案可以包括连接到接地端子的中心部分。因此，具有EOS保护的晶体管，钳位装置和包括该晶体管的ESD保护电路可以增加钳位装置的导通时间，并且可以通过包括配置有栅极的导电图案来充分地放电由于EOS引起的电荷，以蜿蜒的形状相对于彼此连接。

3. 发明授权

US07417282B2 Vertical double-diffused metal oxide semiconductor (VDMOS) device incorporating reverse diode 有权
标题翻译：掺有反向二极管的垂直双扩散金属氧化物半导体（VDMOS）器件
公开(公告)号：US07417282B2
公开(公告)日：2008-08-26
申请号：US11265583
申请日：2005-11-02
申请人： Sung-Pil Jang , Han-Gu Kim , Chan-Hee Jeon
发明人： Sung-Pil Jang , Han-Gu Kim , Chan-Hee Jeon
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7809 , H01L29/42368 , H01L29/7805
摘要： The present invention disclosed herein is a Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) device incorporating a reverse diode. This device includes a plurality of source regions isolated from a drain region. A source region in close proximity to the drain region is a first diffusion structure in which a heavily doped diffusion layer of a second conductivity type is formed in a body region of a second conductivity type. Another source region is a second diffusion structure in which a heavily doped diffusion layer of a first conductivity type and a heavily doped diffusion layer of the second conductivity type are formed in the body region of the second conductivity type. An impurity diffusion structure of the source region in close proximity to the drain region is changed to be operated as a diode, thereby forming a strong current path to ESD (Electro-Static Discharge) or EOS (Electrical Over Stress). As a result, it is possible to prevent the device from being broken down.
摘要翻译：本文公开的本发明是包含反向二极管的垂直双扩散金属氧化物半导体（VDMOS）器件。该器件包括从漏极区域隔离的多个源极区域。靠近漏极区域的源极区域是第一扩散结构，其中在第二导电类型的体区域中形成第二导电类型的重掺杂扩散层。另一个源区是第二扩散结构，其中在第二导电类型的体区中形成第一导电类型的重掺杂扩散层和第二导电类型的重掺杂扩散层。改变靠近漏区的源极区的杂质扩散结构作为二极管工作，从而形成ESD（静电放电）或EOS（电过压）的强电流路径。结果，可以防止装置分解。

4. 发明授权

US08358490B2 Transistor with EOS protection and ESD protection circuit including the same 有权
标题翻译：具有EOS保护和ESD保护电路的晶体管包括相同
公开(公告)号：US08358490B2
公开(公告)日：2013-01-22
申请号：US12213231
申请日：2008-06-17
申请人： Chan-Hee Jeon , Kyoung-Sik Im , Hyun-Jun Choi , Han-Gu Kim
发明人： Chan-Hee Jeon , Kyoung-Sik Im , Hyun-Jun Choi , Han-Gu Kim
IPC分类号： H02H9/00 , H02H3/20 , H02H9/04
CPC分类号： H01L27/0285 , H01L29/0692 , H01L29/0847 , H01L29/4238 , H01L29/78
摘要： A transistor with an electrical overstress (EOS) protection may include an active region, a plurality of impurity regions and a conduction pattern. The active region may be formed in a substrate. The impurity regions may be formed in the active region and arranged at a predetermined or given distance with respect to each other. The conduction pattern may be arranged between each of the impurity regions in a meandering shape, and the conduction pattern may include a center portion connected to a ground terminal. Therefore, a transistor with EOS protection, a clamp device, and an ESD protection circuit including the same may increase an on-time of a clamp device and may sufficiently discharge a charge due to the EOS by including a conduction pattern configured with gates that are connected with respect to each other in a meandering shape.
摘要翻译：具有电应力（EOS）保护的晶体管可以包括有源区，多个杂质区和导电图。有源区可以形成在衬底中。杂质区域可以形成在有源区域中并相对于彼此以预定或给定的距离布置。导电图案可以以蜿蜒的形状布置在每个杂质区之间，并且导电图案可以包括连接到接地端子的中心部分。因此，具有EOS保护的晶体管，钳位装置和包括该晶体管的ESD保护电路可以增加钳位装置的导通时间，并且可以通过包括配置有栅极的导通图案来充分地放电由于EOS引起的电荷，以蜿蜒的形状相对于彼此连接。

5. 发明申请

US20060124994A1 Vertical double-diffused metal oxide semiconductor (VDMOS) device incorporating reverse diode 有权
标题翻译：掺有反向二极管的垂直双扩散金属氧化物半导体（VDMOS）器件
公开(公告)号：US20060124994A1
公开(公告)日：2006-06-15
申请号：US11265583
申请日：2005-11-02
申请人： Sung-Pil Jang , Han-Gu Kim , Chan-Hee Jeon
发明人： Sung-Pil Jang , Han-Gu Kim , Chan-Hee Jeon
IPC分类号： H01L29/76
CPC分类号： H01L29/7809 , H01L29/42368 , H01L29/7805
摘要： The present invention disclosed herein is a Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) device incorporating a reverse diode. This device includes a plurality of source regions isolated from a drain region. A source region in close proximity to the drain region is a first diffusion structure in which a heavily doped diffusion layer of a second conductivity type is formed in a body region of a second conductivity type. Another source region is a second diffusion structure in which a heavily doped diffusion layer of a first conductivity type and a heavily doped diffusion layer of the second conductivity type are formed in the body region of the second conductivity type. An impurity diffusion structure of the source region in close proximity to the drain region is changed to be operated as a diode, thereby forming a strong current path to ESD (Electro-Static Discharge) or EOS (Electrical Over Stress). As a result, it is possible to prevent the device from being broken down.
摘要翻译：本文公开的本发明是包含反向二极管的垂直双扩散金属氧化物半导体（VDMOS）器件。该器件包括从漏极区域隔离的多个源极区域。靠近漏极区域的源极区域是第一扩散结构，其中在第二导电类型的体区域中形成第二导电类型的重掺杂扩散层。另一个源区是第二扩散结构，其中在第二导电类型的体区中形成第一导电类型的重掺杂扩散层和第二导电类型的重掺杂扩散层。改变靠近漏极区的源极区的杂质扩散结构作为二极管工作，从而形成ESD（静电放电）或EOS（电过压）的强电流路径。结果，可以防止装置分解。

6. 发明申请

US20090080129A1 Semiconductor chips having improved electrostatic discharge protection circuit arrangement 有权
标题翻译：具有改善的静电放电保护电路布置的半导体芯片
公开(公告)号：US20090080129A1
公开(公告)日：2009-03-26
申请号：US12292026
申请日：2008-11-10
申请人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
发明人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
IPC分类号： H02H9/00 , H01L23/62
CPC分类号： H01L23/60 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.
摘要翻译：半导体芯片可以包括布置在至少第一和第二行中的多个焊盘以及连接到多个焊盘的多个保护电路。多个保护电路可以包括至少一个二极管。第一保护电路可以连接到第一排焊盘中的第一焊盘，并且第二保护电路可以连接到第二排焊盘中的第二焊盘。第一和第二保护电路可以布置在第一排焊盘的下方。

7. 发明授权

US07898034B2 Semiconductor chips having improved electrostatic discharge protection circuit arrangement 有权
标题翻译：具有改善的静电放电保护电路布置的半导体芯片
公开(公告)号：US07898034B2
公开(公告)日：2011-03-01
申请号：US12292026
申请日：2008-11-10
申请人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
发明人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
IPC分类号： H01L23/62
CPC分类号： H01L23/60 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.
摘要翻译：半导体芯片可以包括布置在至少第一和第二行中的多个焊盘以及连接到多个焊盘的多个保护电路。多个保护电路可以包括至少一个二极管。第一保护电路可以连接到第一排焊盘中的第一焊盘，并且第二保护电路可以连接到第二排焊盘中的第二焊盘。第一和第二保护电路可以布置在第一排焊盘的下方。

8. 发明申请

US20070176241A1 Semiconductor chips having improved electrostatic discharge protection circuit arrangement 有权
标题翻译：具有改善的静电放电保护电路布置的半导体芯片
公开(公告)号：US20070176241A1
公开(公告)日：2007-08-02
申请号：US11654638
申请日：2007-01-18
申请人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
发明人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
IPC分类号： H01L23/62
CPC分类号： H01L23/60 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.
摘要翻译：半导体芯片可以包括布置在至少第一和第二行中的多个焊盘以及连接到多个焊盘的多个保护电路。多个保护电路可以包括至少一个二极管。第一保护电路可以连接到第一排焊盘中的第一焊盘，并且第二保护电路可以连接到第二排焊盘中的第二焊盘。第一和第二保护电路可以布置在第一排焊盘的下方。

9. 发明授权

US07465993B2 Semiconductor chips having improved electrostatic discharge protection circuit arrangement 有权
标题翻译：具有改善的静电放电保护电路布置的半导体芯片
公开(公告)号：US07465993B2
公开(公告)日：2008-12-16
申请号：US11654638
申请日：2007-01-18
申请人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
发明人： Ki-Tae Lee , Han-Gu Kim , Jae-Hyok Ko
IPC分类号： H01L23/62
CPC分类号： H01L23/60 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.
摘要翻译：半导体芯片可以包括布置在至少第一和第二行中的多个焊盘以及连接到多个焊盘的多个保护电路。多个保护电路可以包括至少一个二极管。第一保护电路可以连接到第一排焊盘中的第一焊盘，并且第二保护电路可以连接到第二排焊盘中的第二焊盘。第一和第二保护电路可以布置在第一排焊盘的下方。

10. 发明申请

US20160163690A1 ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND ELECTRONIC DEVICE HAVING THE SAME 有权
标题翻译：静电放电保护装置和具有该静电放电保护装置的电子装置
公开(公告)号：US20160163690A1
公开(公告)日：2016-06-09
申请号：US14809299
申请日：2015-07-27
申请人： Jae-Hyok Ko , Han-Gu Kim , Han-Gu Kim , Jong-Kyu Song , Jin Heo
发明人： Jae-Hyok Ko , Han-Gu Kim , Han-Gu Kim , Jong-Kyu Song , Jin Heo
IPC分类号： H01L27/02 , H01L29/06 , H01L29/36 , H01L29/10
CPC分类号： H01L27/0262 , H01L27/027
摘要： In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.
摘要翻译：在ESD保护装置中，第一导电类型的第一阱和第二导电类型的第二阱形成在基板中以彼此接触。第一导电类型的第一杂质区和第二导电类型的第二杂质区形成在第一阱中，并且电连接到第一电极焊盘。第二杂质区域在第二阱的方向上与第一杂质区间隔开。在第二阱中形成第三杂质区，具有第二导电类型，并且电连接到第二电极焊盘。在第二阱中形成第四杂质区，位于第一阱的从第三杂质区方向接触第三杂质区，具有第一导电类型，并且是电漂浮的。

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