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1. 发明授权

US10163976B2 Magnetoresistive random access memory device and method of manufacturing the same 有权
公开(公告)号：US10163976B2
公开(公告)日：2018-12-25
申请号：US15712130
申请日：2017-09-21
申请人： Ki-Seok Suh , Jae-Chul Shim , Kil-Ho Lee , Yong-Seok Chung , Gwan-Hyeob Koh , Yoon-Jong Song
发明人： Ki-Seok Suh , Jae-Chul Shim , Kil-Ho Lee , Yong-Seok Chung , Gwan-Hyeob Koh , Yoon-Jong Song
IPC分类号： H01L27/22 , H01L43/12
摘要： A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.

2. 发明授权

US09853087B2 Magnetoresistive random access memory device and method of manufacturing the same 有权
公开(公告)号：US09853087B2
公开(公告)日：2017-12-26
申请号：US15157403
申请日：2016-05-17
申请人： Ki-Seok Suh , Jae-Chul Shim , Kil-Ho Lee , Yong-Seok Chung , Gwan-Hyeob Koh , Yoon-Jong Song
发明人： Ki-Seok Suh , Jae-Chul Shim , Kil-Ho Lee , Yong-Seok Chung , Gwan-Hyeob Koh , Yoon-Jong Song
IPC分类号： H01L27/22 , H01L43/12
CPC分类号： H01L27/222 , H01L43/12
摘要： A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.

3. 发明申请

US20170054070A1 Magnetoresistive Random Access Memory Device and Method of Manufacturing the Same 审中-公开
标题翻译：磁阻随机存取存储器件及其制造方法
公开(公告)号：US20170054070A1
公开(公告)日：2017-02-23
申请号：US15146355
申请日：2016-05-04
申请人： Jung-Hoon Bak , Myoung-Su Son , Jae-Chul Shim , Gwan-Hyeob Koh , Yoon-Jong Song
发明人： Jung-Hoon Bak , Myoung-Su Son , Jae-Chul Shim , Gwan-Hyeob Koh , Yoon-Jong Song
IPC分类号： H01L43/02 , H01L43/10 , H01L43/12 , H01L43/08
CPC分类号： H01L43/02 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/12
摘要： In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.
摘要翻译：在制造MRAM器件的方法中，在衬底上形成包括下电极，MTJ结构和顺序层叠的上电极的存储单元。在衬底上形成包括依次堆叠的覆盖层，牺牲层和蚀刻停止层的保护层结构以覆盖存储单元。在保护层结构上形成绝缘中间层。形成绝缘中间层以形成露出保护层结构的开口。暴露的保护层结构被部分去除以暴露上电极。在暴露的上电极上形成布线以填充开口。

4. 发明授权

US10056543B2 Magnetoresistive random access memory device having magnetic tunnel junction and method of manufacturing the same 有权
公开(公告)号：US10056543B2
公开(公告)日：2018-08-21
申请号：US15146355
申请日：2016-05-04
申请人： Jung-Hoon Bak , Myoung-Su Son , Jae-Chul Shim , Gwan-Hyeob Koh , Yoon-Jong Song
发明人： Jung-Hoon Bak , Myoung-Su Son , Jae-Chul Shim , Gwan-Hyeob Koh , Yoon-Jong Song
IPC分类号： H01L21/00 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12
CPC分类号： H01L43/02 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/12
摘要： In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.

5. 发明授权

US08026543B2 Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same 有权
标题翻译：具有相变存储单元的半导体器件，使用该半导体器件的电子系统及其制造方法
公开(公告)号：US08026543B2
公开(公告)日：2011-09-27
申请号：US12338814
申请日：2008-12-18
申请人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
发明人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC分类号： H01L27/108 , H01L47/00
CPC分类号： H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
摘要： A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material pattern, and an oxidation barrier of electrically insulative material. The molding layer has a protrusion at its upper portion. One portion of the phase-changeable material pattern overlies the protrusion of the molding layer, and another portion of the phase-changeable material pattern extends through the protrusion. The electrically insulative material of the oxidation barrier may cover the phase-changeable material pattern and/or extend along and cover the entire area at which the protrusion of the molding layer and the portion of the phase-change material pattern disposed on the protrusion adjoin.
摘要翻译：相变存储器件具有氧化阻挡层以防止存储器细胞污染或氧化。在一个实施例中，半导体存储器件包括设置在半导体衬底上的成型层，相变材料图案和电绝缘材料的氧化屏障。成型层在其上部具有突出部。可相变材料图案的一部分覆盖模制层的突起，并且相变材料图案的另一部分延伸穿过突出部。氧化屏障的电绝缘材料可以覆盖相变材料图案和/或延伸并且覆盖模制层的突起和设置在突起上的相变材料图案的部分邻接的整个区域。

6. 发明申请

US20090101881A1 SEMICONDUCTOR DEVICES HAVING PHASE CHANGE MEMORY CELLS, ELECTRONIC SYSTEMS EMPLOYING THE SAME AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有相变记忆体的半导体器件，使用其的电子系统及其制造方法
公开(公告)号：US20090101881A1
公开(公告)日：2009-04-23
申请号：US12338814
申请日：2008-12-18
申请人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
发明人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC分类号： H01L45/00
CPC分类号： H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
摘要： In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.
摘要翻译：在一个实施例中，相变存储器件具有防止存储器单元污染或氧化的氧化阻挡层及其制造方法。在一个实施例中，半导体存储器件包括覆盖半导体衬底的成型层。模制层具有从其顶表面垂直延伸的突出部分。该装置还包括与突出部分相邻的相变材料图案和与相变材料图案电连接的下部电极。

7. 发明申请

US20050263829A1 Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same 有权
标题翻译：具有相变存储单元的半导体器件，使用该半导体器件的电子系统及其制造方法
公开(公告)号：US20050263829A1
公开(公告)日：2005-12-01
申请号：US11139283
申请日：2005-05-27
申请人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
发明人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC分类号： H01L21/00 , H01L21/336 , H01L27/24 , H01L29/00 , H01L29/78
CPC分类号： H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
摘要： In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.
摘要翻译：在一个实施例中，相变存储器件具有防止存储器单元污染或氧化的氧化阻挡层及其制造方法。在一个实施例中，半导体存储器件包括覆盖半导体衬底的成型层。模制层具有从其顶表面垂直延伸的突出部分。该装置还包括与突出部分相邻的相变材料图案和与相变材料图案电连接的下部电极。

8. 发明授权

US07482616B2 Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same 有权
标题翻译：具有相变存储单元的半导体器件，使用该半导体器件的电子系统及其制造方法
公开(公告)号：US07482616B2
公开(公告)日：2009-01-27
申请号：US11139283
申请日：2005-05-27
申请人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
发明人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC分类号： H01L29/02
CPC分类号： H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
摘要： In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.
摘要翻译：在一个实施例中，相变存储器件具有防止存储器单元污染或氧化的氧化阻挡层及其制造方法。在一个实施例中，半导体存储器件包括覆盖半导体衬底的成型层。模制层具有从其顶表面垂直延伸的突出部分。该装置还包括与突出部分相邻的相变材料图案和与相变材料图案电连接的下部电极。

9. 发明申请

US20120236627A1 MULTI-LEVEL MEMORY DEVICES AND METHODS OF OPERATING THE SAME 有权
标题翻译：多级存储器件及其操作方法
公开(公告)号：US20120236627A1
公开(公告)日：2012-09-20
申请号：US13487463
申请日：2012-06-04
申请人： Gwan-Hyeob Koh , Dae-Won Ha
发明人： Gwan-Hyeob Koh , Dae-Won Ha
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C11/56 , G11C13/0004
摘要： The present invention provides a multi-level memory device and method of operating the same. The device comprises a memory structure in which a distribution density of resistance levels around its minimum value is higher than that around its maximum value.
摘要翻译：本发明提供了一种多级存储装置及其操作方法。该装置包括存储器结构，其中电阻值在其最小值附近的分布密度高于围绕其最大值的分布密度。

10. 发明授权

US07112492B2 Methods of fabricating semiconductor devices with scalable two transistor memory cells 失效
标题翻译：用可扩展的双晶体管存储单元制造半导体器件的方法
公开(公告)号：US07112492B2
公开(公告)日：2006-09-26
申请号：US11040229
申请日：2005-01-21
申请人： Su-Jin Ahn , Gwan-Hyeob Koh , Hyoung-Joon Kim
发明人： Su-Jin Ahn , Gwan-Hyeob Koh , Hyoung-Joon Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11543 , H01L29/42324 , H01L29/7881
摘要： Semiconductor devices having scalable two transistor memory cells, and methods of fabricating the same, are disclosed. The semiconductor devices include a semiconductor substrate having first, second and third isolation layers thereon. The first and second isolation layers are spaced apart to define a first active region therebetween, and the second and third isolation layers are likewise spaced apart to form a second active region therebetween. A cell gate is provided on each active region that includes a gate dielectric layer, a storage node, a multiple tunnel junction barrier and a source layer that are sequentially stacked. The device also includes first and second control lines that surround at least a portion of each sidewall of the cell gates. A dielectric layer may be interposed between the sidewalls of the cell gates and the control line that surrounds it. A data line connects to the cell gates.
摘要翻译：公开了具有可伸缩的双晶体管存储单元的半导体器件及其制造方法。半导体器件包括其上具有第一，第二和第三隔离层的半导体衬底。第一和第二隔离层间隔开以限定它们之间的第一有源区，并且第二隔离层和第三隔离层同样隔开以在它们之间形成第二有源区。在每个有源区域上提供一个单元栅极，该栅极电介质层，存储节点，多个隧道结屏障和源层依次堆叠。该装置还包括围绕电池栅极的每个侧壁的至少一部分的第一和第二控制线。电介质层可以插在电池栅极的侧壁和围绕它的控制线之间。数据线连接到单元门。

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