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1. 发明授权

US07327184B2 Low-power multi-level pulse amplitude modulation driver and semiconductor device having the driver 有权
标题翻译：具有驱动器的低功率多电平脉冲幅度调制驱动器和半导体器件
公开(公告)号：US07327184B2
公开(公告)日：2008-02-05
申请号：US11454746
申请日：2006-06-16
申请人： Ki-Hyuk Sung , Chi-Won Kim
发明人： Ki-Hyuk Sung , Chi-Won Kim
IPC分类号： G06F7/44
CPC分类号： H03M5/20 , H03M1/002 , H03M1/745
摘要： A low-power multi-level pulse amplitude modulation (PAM) driver, and a semiconductor device having the same, in which the multi (M)-level PAM driver includes a load unit, first and second current sources, a pair of first input transistors, a pair of second input transistors, and a current source controller, where M is an integer greater than 3. The load unit is electrically connected to an output terminal, and the first and second current sources respectively supply a first amount of current and a second amount of current to the load unit. The pair of first input transistors electrically connects the first current source and the load unit in response to a first bit signal, and the pair of the second input transistors electrically connects the second current source and the load unit in response to a second bit signal. The current source controller activates or deactivates one of the first and second current sources in response to the first and second bit signals. Accordingly, current sources for a multi-level PAM driver are selectively activated or deactivated, thereby minimizing power consumption in the multi-level PAM driver.
摘要翻译：低功率多电平脉冲幅度调制（PAM）驱动器和具有该低功率多电平脉冲幅度调制（PAM）驱动器的半导体器件，其中多（M）级PAM驱动器包括负载单元，第一和第二电流源，一对第一输入晶体管，一对第二输入晶体管和电流源控制器，其中M是大于3的整数。负载单元电连接到输出端，并且第一和第二电流源分别提供第一量的电流和第二量的电流到负载单元。一对第一输入晶体管响应于第一位信号而电连接第一电流源和负载单元，并且该对第二输入晶体管响应于第二位信号而电连接第二电流源和负载单元。电流源控制器响应于第一和第二位信号激活或去激活第一和第二电流源之一。因此，多级PAM驱动器的电流源被选择性地激活或去激活，从而最小化多电平PAM驱动器中的功耗。

2. 发明申请

US20070052455A1 Low-power multi-level pulse amplitude modulation driver and semiconductor device having the driver 有权
标题翻译：具有驱动器的低功率多电平脉冲幅度调制驱动器和半导体器件
公开(公告)号：US20070052455A1
公开(公告)日：2007-03-08
申请号：US11454746
申请日：2006-06-16
申请人： Ki-Hyuk Sung , Chi-Won Kim
发明人： Ki-Hyuk Sung , Chi-Won Kim
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03M5/20 , H03M1/002 , H03M1/745
摘要： A low-power multi-level pulse amplitude modulation (PAM) driver, and a semiconductor device having the same, in which the multi (M)-level PAM driver includes a load unit, first and second current sources, a pair of first input transistors, a pair of second input transistors, and a current source controller, where M is an integer greater than 3. The load unit is electrically connected to an output terminal, and the first and second current sources respectively supply a first amount of current and a second amount of current to the load unit. The pair of first input transistors electrically connects the first current source and the load unit in response to a first bit signal, and the pair of the second input transistors electrically connects the second current source and the load unit in response to a second bit signal. The current source controller activates or deactivates one of the first and second current sources in response to the first and second bit signals. Accordingly, current sources for a multi-level PAM driver are selectively activated or deactivated, thereby minimizing power consumption in the multi-level PAM driver.
摘要翻译：低功率多电平脉冲幅度调制（PAM）驱动器和具有该低功率多电平脉冲幅度调制（PAM）驱动器的半导体器件，其中多（M）级PAM驱动器包括负载单元，第一和第二电流源，一对第一输入晶体管，一对第二输入晶体管和电流源控制器，其中M是大于3的整数。负载单元电连接到输出端，并且第一和第二电流源分别提供第一量的电流和第二量的电流到负载单元。一对第一输入晶体管响应于第一位信号而电连接第一电流源和负载单元，并且该对第二输入晶体管响应于第二位信号而电连接第二电流源和负载单元。电流源控制器响应于第一和第二位信号激活或去激活第一和第二电流源之一。因此，多级PAM驱动器的电流源被选择性地激活或去激活，从而最小化多电平PAM驱动器中的功耗。

3. 发明授权

US07696834B2 Voltage controlled oscillator and method capable of reducing phase noise and jitter with startup gain 失效
标题翻译：压控振荡器和方法能够降低启动增益时的相位噪声和抖动
公开(公告)号：US07696834B2
公开(公告)日：2010-04-13
申请号：US11757459
申请日：2007-06-04
申请人： Ki-Hyuk Sung
发明人： Ki-Hyuk Sung
IPC分类号： H03L5/00
CPC分类号： H03L7/099 , H03B5/06 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/129 , H03L5/00 , H03L7/10
摘要： A voltage-controlled oscillator includes: a bias voltage generator operating to generate first and second bias voltages in response to a control signal; a voltage-controlled oscillation circuit connected to a control node and configured to generate oscillation signals in response to an input voltage; a selection signal generator operating to generate a selection signal in response each to the oscillation signals; and a selection circuit operating to select one of the first and second bias voltages in response to the selection signal and outputting the selected bias voltage to the control node.
摘要翻译：压控振荡器包括：偏置电压发生器，用于响应于控制信号产生第一和第二偏置电压; 连接到控制节点并被配置为响应于输入电压产生振荡信号的压控振荡电路; 操作用于响应于所述振荡信号产生选择信号的选择信号发生器; 以及选择电路，其操作以响应于所述选择信号选择所述第一和第二偏置电压之一并将所选择的偏置电压输出到所述控制节点。

4. 发明申请

US20080068097A1 VOLTAGE CONTROLLED OSCILLATOR AND METHOD CAPABLE OF REDUCING PHASE NOISE AND JITTER WITH STARTUP GAIN 失效
标题翻译：电压控制振荡器和能够减少相位噪声的抖动和具有启动增益的抖动
公开(公告)号：US20080068097A1
公开(公告)日：2008-03-20
申请号：US11757459
申请日：2007-06-04
申请人： Ki-Hyuk Sung
发明人： Ki-Hyuk Sung
IPC分类号： H03L7/099 , H03B5/12 , H03L5/00
CPC分类号： H03L7/099 , H03B5/06 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/129 , H03L5/00 , H03L7/10
摘要： A voltage-controlled oscillator includes: a bias voltage generator operating to generate first and second bias voltages in response to a control signal; a voltage-controlled oscillation circuit connected to a control node and configured to generate oscillation signals in response to an input voltage; a selection signal generator operating to generate a selection signal in response each to the oscillation signals; and a selection circuit operating to select one of the first and second bias voltages in response to the selection signal and outputting the selected bias voltage to the control node.
摘要翻译：压控振荡器包括：偏置电压发生器，用于响应于控制信号产生第一和第二偏置电压; 连接到控制节点并被配置为响应于输入电压产生振荡信号的压控振荡电路; 操作用于响应于所述振荡信号产生选择信号的选择信号发生器; 以及选择电路，其操作以响应于所述选择信号选择所述第一和第二偏置电压之一并将所选择的偏置电压输出到所述控制节点。

5. 发明授权

US06615398B2 Method for dividing ROM and DDFS using the same method 有权
公开(公告)号：US06615398B2
公开(公告)日：2003-09-02
申请号：US10017315
申请日：2001-12-18
申请人： Hyun Kyu Yu , Seon-Ho Han , Mun Yang Park , Seong-Do Kim , Yong-Sik Youn , Lee-Sup Kim , Ki-Hyuk Sung , Byung-Do Yang , Young-Jun Kim
发明人： Hyun Kyu Yu , Seon-Ho Han , Mun Yang Park , Seong-Do Kim , Yong-Sik Youn , Lee-Sup Kim , Ki-Hyuk Sung , Byung-Do Yang , Young-Jun Kim
IPC分类号： G06F1750
CPC分类号： G06F1/0356 , G06F1/0328 , G06F2101/04 , G11C17/00
摘要： The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e., coarse-quantized ROM, coarse-error ROM, fine-quantized ROM and fine-error ROM.

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