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1. 发明授权

US5523706A High speed, low power macrocell 失效
标题翻译：高速，低功率的宏单元
公开(公告)号：US5523706A
公开(公告)日：1996-06-04
申请号：US401046
申请日：1995-03-08
申请人： Khusrow Kiani , Janusz K. Balicki , Behzad Nouban , Ken Li
发明人： Khusrow Kiani , Janusz K. Balicki , Behzad Nouban , Ken Li
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17716 , H03K19/1736
摘要： A macrocell for use in a programmable logic device (PLD) providing for enhanced logic capability and reduced setup time. The preferred embodiment of the macrocell includes two look-up tables, for increased fan-in, and two flip-flops that increase fan-out, thereby doubling logic capability of the PLD without unacceptably increasing device size. Doubling the register count makes this PLD particularly suitable for applications employing high density sequential logic. Furthermore, a second register can be used for receiving fast input signals form an input to the PLD to reduce setup time.
摘要翻译：用于可编程逻辑器件（PLD）的宏单元，提供增强的逻辑能力和缩短的建立时间。宏单元的优选实施例包括用于增加扇入的两个查找表，以及增加扇出的两个触发器，从而使PLD的逻辑能力加倍，而不增加设备大小。将寄存器数量加倍使得该PLD特别适用于采用高密度序列逻辑的应用。此外，第二寄存器可用于从PLD的输入接收快速输入信号以减少建立时间。

2. 发明授权

US5399922A Macrocell comprised of two look-up tables and two flip-flops 失效
标题翻译：宏单元由两个查找表和两个触发器组成
公开(公告)号：US5399922A
公开(公告)日：1995-03-21
申请号：US086420
申请日：1993-07-02
申请人： Khusrow Kiani , Janusz K. Balicki , Behzad Nouban , Ken Li
发明人： Khusrow Kiani , Janusz K. Balicki , Behzad Nouban , Ken Li
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17716 , H03K19/1736
摘要： A macrocell for use in a programmable logic device (PLD) providing for enhanced logic capability and reduced setup time. The preferred embodiment of the macrocell includes two look-up tables, for increased fan-in, and two flip-flops that increase fan-out, thereby doubling logic capability of the PLD without unacceptably increasing device size. Doubling the register count makes this PLD particularly suitable for applications employing high density sequential logic. Furthermore, a second register can be used for receiving fast input signals form an input to the PLD to reduce setup time.
摘要翻译：用于可编程逻辑器件（PLD）的宏单元，提供增强的逻辑能力和缩短的建立时间。宏单元的优选实施例包括用于增加扇入的两个查找表，以及增加扇出的两个触发器，从而使PLD的逻辑能力加倍，而不增加设备大小。将寄存器数量加倍使得该PLD特别适用于采用高密度序列逻辑的应用。此外，第二寄存器可用于从PLD的输入接收快速输入信号以减少建立时间。

3. 发明授权

US07245147B1 Interface for a programmable logic device 有权
标题翻译：可编程逻辑器件的接口
公开(公告)号：US07245147B1
公开(公告)日：2007-07-17
申请号：US11119375
申请日：2005-04-29
申请人： Behzad Nouban , Toan D. Doan , Pooyan Khoshkoo
发明人： Behzad Nouban , Toan D. Doan , Pooyan Khoshkoo
IPC分类号： H03K19/173
CPC分类号： H03K19/1774 , H03K19/17744
摘要： The present invention provides circuitry for implementing a multiple data rate interface architectures for programmable logic devices. The programmable logic device of the invention includes a core and surrounding periphery. The core includes a plurality of logic elements arranged in an array. Some of the logic elements within the core include registers that are used as data registers for the multiple data rate interface.
摘要翻译：本发明提供用于实现可编程逻辑器件的多数据速率接口架构的电路。本发明的可编程逻辑器件包括一个核心和周围的周边。核心包括以阵列布置的多个逻辑元件。核心中的一些逻辑元件包括用作多数据速率接口的数据寄存器的寄存器。

4. 发明授权

US06894531B1 Interface for a programmable logic device 有权
标题翻译：可编程逻辑器件的接口
公开(公告)号：US06894531B1
公开(公告)日：2005-05-17
申请号：US10444741
申请日：2003-05-22
申请人： Behzad Nouban , Toan D. Do , Pooyan Khoshkhoo
发明人： Behzad Nouban , Toan D. Do , Pooyan Khoshkhoo
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1774 , H03K19/17744
摘要： The present invention provides circuitry for implementing a multiple data rate interface architectures for programmable logic devices. The programmable logic device of the invention includes a core and surrounding periphery. The core includes a plurality of logic elements arranged in an array. Some of the logic elements within the core include registers that are used as data registers for the multiple data rate interface.
摘要翻译：本发明提供用于实现可编程逻辑器件的多数据速率接口架构的电路。本发明的可编程逻辑器件包括一个核心和周围的周边。核心包括以阵列布置的多个逻辑元件。核心中的一些逻辑元件包括用作多数据速率接口的数据寄存器的寄存器。

5. 发明授权

US06369613B1 Input/output drivers 有权
标题翻译：输入/输出驱动器
公开(公告)号：US06369613B1
公开(公告)日：2002-04-09
申请号：US09558537
申请日：2000-04-26
申请人： John Costello , Behzad Nouban
发明人： John Costello , Behzad Nouban
IPC分类号： H03K190175
CPC分类号： H03K19/00315 , H03K19/018585
摘要： A technique is provided for improving the output drive capacity of output drivers on an integrated circuit that is configured to support I/O standards having operating voltages greater than the intrinsic core supply voltage. When MOS field-effect transistors are used in the I/O circuitry of such integrated circuits, the gate oxide layers of the transistors in the interface circuitry may need to be thicker than those comprising the core circuitry in order to tolerate I/O voltages that exceed the core supply voltage. In counteracting the degradation in output drive that may result from thickening the gate oxide layer, the pull-down signal applied to the gate of the pull-down transistor is preferably level-shifted from the core supply voltage to the higher external operating voltage associated with the I/O standard being supported. This external voltage is made available to the level-shifting circuit preferably through a spare pin or a gated I/O pin.
摘要翻译：提供了一种技术，用于提高集成电路中输出驱动器的输出驱动能力，该集成电路被配置为支持具有大于本征核心电源电压的工作电压的I / O标准。当在这种集成电路的I / O电路中使用MOS场效应晶体管时，接口电路中的晶体管的栅极氧化物层可能需要比包含核心电路的晶体管的栅极氧化物层厚，以便容忍I / O电压超过核心电源电压。在抵消可能由栅极氧化物层增厚引起的输出驱动中的劣化时，施加到下拉晶体管的栅极的下拉信号优选地从芯供电电压电平移位到与支持I / O标准。该外部电压优选地通过备用引脚或门控I / O引脚可用于电平移位电路。

6. 发明授权

US5200920A Method for programming programmable elements in programmable devices 失效
标题翻译：在可编程器件中编程可编程元件的方法
公开(公告)号：US5200920A
公开(公告)日：1993-04-06
申请号：US759944
申请日：1991-09-17
申请人： Kevin A. Norman , James D. Sansbury , Alan L. Herrmann , Matthew C. Hendricks , Behzad Nouban
发明人： Kevin A. Norman , James D. Sansbury , Alan L. Herrmann , Matthew C. Hendricks , Behzad Nouban
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454
摘要： A method for programming programmable EPROM elements in programmable logic arrays. Multiple programming passes are made through the array, with the programming pulses decreasing in duration on each pass.
摘要翻译：用于在可编程逻辑阵列中编程可编程EPROM元件的方法。通过阵列进行多个编程遍历，编程脉冲在每次通过时持续时间减少。

7. 发明授权

US5057712A Address transition detector for programmable logic array 失效
标题翻译：用于可编程逻辑阵列的地址转换检测器
公开(公告)号：US5057712A
公开(公告)日：1991-10-15
申请号：US414312
申请日：1989-09-29
申请人： Cuong Trinh , Vincent K. Z. Win , Behzad Nouban , Andrew K. Chan
发明人： Cuong Trinh , Vincent K. Z. Win , Behzad Nouban , Andrew K. Chan
IPC分类号： H03K5/1534 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/17704 , H03K19/17784 , H03K5/1534
摘要： An improved address transition detector for use in PAL circuits is disclosed. The invention provides a predetermined logical output on a transition detection signal (TDS) bus for a transition of the input address on an input pad of the PAL. The TDS bus is used to trigger a phi generator which controls sense amplifiers and latch blocks on the PAL such that the circuitry is maintained in a low power stand-by mode. The detector includes a first inverter for buffering the address input to provide a first signal, a second inverter for inverting the first signal to provide a second signal and a comparator for providing the predetermined logical level on the TDS bus for a period of time after the first signal and the second signal have changed states.
摘要翻译：公开了一种用于PAL电路的改进的地址转换检测器。本发明在转移检测信号（TDS）总线上提供预定的逻辑输出，用于在PAL的输入焊盘上转换输入地址。 TDS总线用于触发在PAL上控制读出放大器和锁存块的phi发生器，使电路保持在低功率待机模式。检测器包括用于缓冲地址输入以提供第一信号的第一反相器，用于反转第一信号以提供第二信号的第二反相器和用于在TDS总线上提供预定逻辑电平一段时间之后的第二反相器第一信号和第二信号已经改变状态。

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