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1. 发明授权

US5523706A High speed, low power macrocell 失效
标题翻译：高速，低功率的宏单元
公开(公告)号：US5523706A
公开(公告)日：1996-06-04
申请号：US401046
申请日：1995-03-08
申请人： Khusrow Kiani , Janusz K. Balicki , Behzad Nouban , Ken Li
发明人： Khusrow Kiani , Janusz K. Balicki , Behzad Nouban , Ken Li
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17716 , H03K19/1736
摘要： A macrocell for use in a programmable logic device (PLD) providing for enhanced logic capability and reduced setup time. The preferred embodiment of the macrocell includes two look-up tables, for increased fan-in, and two flip-flops that increase fan-out, thereby doubling logic capability of the PLD without unacceptably increasing device size. Doubling the register count makes this PLD particularly suitable for applications employing high density sequential logic. Furthermore, a second register can be used for receiving fast input signals form an input to the PLD to reduce setup time.
摘要翻译：用于可编程逻辑器件（PLD）的宏单元，提供增强的逻辑能力和缩短的建立时间。宏单元的优选实施例包括用于增加扇入的两个查找表，以及增加扇出的两个触发器，从而使PLD的逻辑能力加倍，而不增加设备大小。将寄存器数量加倍使得该PLD特别适用于采用高密度序列逻辑的应用。此外，第二寄存器可用于从PLD的输入接收快速输入信号以减少建立时间。

2. 发明授权

US5399922A Macrocell comprised of two look-up tables and two flip-flops 失效
标题翻译：宏单元由两个查找表和两个触发器组成
公开(公告)号：US5399922A
公开(公告)日：1995-03-21
申请号：US086420
申请日：1993-07-02
申请人： Khusrow Kiani , Janusz K. Balicki , Behzad Nouban , Ken Li
发明人： Khusrow Kiani , Janusz K. Balicki , Behzad Nouban , Ken Li
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17716 , H03K19/1736
摘要： A macrocell for use in a programmable logic device (PLD) providing for enhanced logic capability and reduced setup time. The preferred embodiment of the macrocell includes two look-up tables, for increased fan-in, and two flip-flops that increase fan-out, thereby doubling logic capability of the PLD without unacceptably increasing device size. Doubling the register count makes this PLD particularly suitable for applications employing high density sequential logic. Furthermore, a second register can be used for receiving fast input signals form an input to the PLD to reduce setup time.
摘要翻译：用于可编程逻辑器件（PLD）的宏单元，提供增强的逻辑能力和缩短的建立时间。宏单元的优选实施例包括用于增加扇入的两个查找表，以及增加扇出的两个触发器，从而使PLD的逻辑能力加倍，而不增加设备大小。将寄存器数量加倍使得该PLD特别适用于采用高密度序列逻辑的应用。此外，第二寄存器可用于从PLD的输入接收快速输入信号以减少建立时间。

3. 发明授权

US5341044A Flexible configuration logic array block for programmable logic devices 失效
标题翻译：用于可编程逻辑器件的灵活配置逻辑阵列块
公开(公告)号：US5341044A
公开(公告)日：1994-08-23
申请号：US49064
申请日：1993-04-19
申请人： Bahram Ahanin , Janusz K. Balicki , Khusrow Kiani , William Leong , Ken-Ming Li , Bezhad Nouban
发明人： Bahram Ahanin , Janusz K. Balicki , Khusrow Kiani , William Leong , Ken-Ming Li , Bezhad Nouban
IPC分类号： H03K19/173
CPC分类号： H03K19/1737
摘要： A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.
摘要翻译：可编程逻辑器件具有多个专用的全局控制输入线，其直接与被称为逻辑阵列块的各个构建块直接连接。这些线可用于时钟，预设，清零或输出使能。来自中心位置的全局互连阵列的其他逻辑信号线通过多路复用器阵列进行选择，然后与逻辑阵列块进行接口。逻辑阵列块中的多路复用器的配置阵列从这些输入中选择产生本地控制输入信号，其最终功能通过在逻辑阵列块内的宏单元级进一步复用来确定。

4. 发明授权

US5473266A Programmable logic device having fast programmable logic array blocks and a central global interconnect array 失效
标题翻译：具有快速可编程逻辑阵列块和中央全局互连阵列的可编程逻辑器件
公开(公告)号：US5473266A
公开(公告)日：1995-12-05
申请号：US324860
申请日：1994-10-18
申请人： Bahram Ahanin , Janusz K. Balicki , Khusrow Kiani , William Leong , Ken-Ming Li , Bezhad Nouban
发明人： Bahram Ahanin , Janusz K. Balicki , Khusrow Kiani , William Leong , Ken-Ming Li , Bezhad Nouban
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1737
摘要： A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.
摘要翻译：可编程逻辑器件具有多个专用的全局控制输入线，其直接与被称为逻辑阵列块的各个构建块直接连接。这些线可用于时钟，预设，清零或输出使能。来自中心位置的全局互连阵列的其他逻辑信号线通过多路复用器阵列进行选择，然后与逻辑阵列块进行接口。逻辑阵列块中的多路复用器的配置阵列从这些输入中选择产生本地控制输入信号，其最终功能通过在逻辑阵列块内的宏单元级进一步复用来确定。

5. 发明授权

US5953537A Method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device 失效
标题翻译：用于减少在可编程逻辑器件中实现查找表所需的可编程架构元件的数量的方法和装置
公开(公告)号：US5953537A
公开(公告)日：1999-09-14
申请号：US259360
申请日：1994-06-14
申请人： Janusz K. Balicki , Bezhad Nouban , Khusrow Kiani
发明人： Janusz K. Balicki , Bezhad Nouban , Khusrow Kiani
IPC分类号： H03K19/173 , H03K19/00
CPC分类号： H03K19/1736
摘要： A method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device. At least one logic function to be performed by the look-up table is chosen. An output state is determined for each set of inputs to the look-up table, the output state being an array of outputs of the look-up table. Each output state is made up of responses of the chosen logic functions to a particular set of input variables. Identical output states are formed into groups. Selected groups of the output states which do not require programmable architecture elements are eliminated. A programmable architecture element is then assigned for each remaining group of output states.
摘要翻译：一种用于减少在可编程逻辑器件中实现查找表所需的可编程架构元件的数量的方法和装置。选择由查找表执行的至少一个逻辑功能。针对查找表的每组输入确定输出状态，输出状态是查找表的输出数组。每个输出状态由所选择的逻辑功能对特定输入变量集合的响应组成。相同的输出状态形成组。消除了不需要可编程架构元件的选择的输出状态组。然后为每个剩余的输出状态组分配可编程架构元素。

6. 发明授权

US06809574B1 Back-drive circuit protection for I/O cells using CMOS process 有权
标题翻译：使用CMOS工艺的I / O单元的背驱电路保护
公开(公告)号：US06809574B1
公开(公告)日：2004-10-26
申请号：US10205975
申请日：2002-07-26
申请人： Khusrow Kiani
发明人： Khusrow Kiani
IPC分类号： G05F110
CPC分类号： H03K19/00315
摘要： In a high tolerance I/O interface with over-voltage protection during 5V tolerant mode and back-drive mode, includes pass gate circuitry to isolate the output of the driver circuit and input of the receiver circuit from the pad voltage during stress mode. The gate voltage of the PMOS transistor of the pass gate is charged up to avoid gate oxide breakdown during stress mode. Also, the gate and well of the driver pull-up transistor are charged to NG1 to avoid current flow through the transistor and to its well.
摘要翻译：在具有5V耐受模式和后驱动模式的过压保护的高容差I / O接口中，包括通过栅极电路，以在应力模式期间将驱动电路的输出和接收器电路的输入与焊盘电压隔离。通过栅极的PMOS晶体管的栅极电压被充电以避免在应力模式期间的栅极氧化物击穿。此外，驱动器上拉晶体管的栅极和阱被充电到NG1，以避免电流流过晶体管及其阱。

7. 发明授权

US08384444B1 I/O driver with pass gate feedback controlled output driver 有权
标题翻译： I / O驱动器具有通过门反馈控制的输出驱动器
公开(公告)号：US08384444B1
公开(公告)日：2013-02-26
申请号：US11218937
申请日：2005-09-03
申请人： Elroy Lucero , Khusrow Kiani
发明人： Elroy Lucero , Khusrow Kiani
IPC分类号： H03K3/00
CPC分类号： H03K19/00361 , H03K19/00 , H03K19/01721
摘要： In an I/O driver, noise reduction is achieved while maintaining good performance, by providing a conventional output driver leg and a secondary output driver leg, the primary output driver leg comprising a primary predriver and a primary output driver, and the secondary output driver leg comprising a secondary output driver having a common output with the primary output driver, wherein feedback from the common output is fed through a pair of pass gates that control the secondary output driver.
摘要翻译：在I / O驱动器中，通过提供传统的输出驱动器支路和辅助输出驱动器支路，实现噪声降低，同时保持良好的性能，主输出驱动器支路包括初级预驱动器和主输出驱动器，次级输出驱动器腿部包括具有与主输出驱动器的公共输出的次级输出驱动器，其中来自公共输出的反馈通过控制次级输出驱动器的一对通过栅极馈送。

8. 发明授权

US07071764B1 Back-drive circuit protection for I/O cells using CMOS process 有权
标题翻译：使用CMOS工艺的I / O单元的背驱电路保护
公开(公告)号：US07071764B1
公开(公告)日：2006-07-04
申请号：US10206541
申请日：2002-07-26
申请人： Khusrow Kiani
发明人： Khusrow Kiani
IPC分类号： H03K3/00
CPC分类号： H01L27/0266 , H03K19/00315
摘要： In a high tolerance I/O interface with over-voltage protection beyond 5 V, a cascoded driver with PMOS pull-up and NMOS pull-down transistors, connected to a pad, is provided. Circuitry is included to maintain the floating well voltages of the PMOS pull-up driver transistors at substantially the same voltages as their respective drains, and their gate voltages at substantially the same voltages as their respective drains, under back-drive and 5 V tolerant mode. Circuitry is also provided to increase the gate voltage of one of a cascoded pair of NMOS pull-down driver transistors, so that the drain-source junction voltage and gate oxide voltage of the transistor will be less than the breakdown voltage under back-drive and 5 V tolerant mode.
摘要翻译：在具有超过5 V的过压保护的高容差I / O接口中，提供了一个连接到焊盘的具有PMOS上拉和NMOS下拉晶体管的级联驱动器。包括电路以保持PMOS上拉驱动晶体管的浮置阱电压与它们各自的漏极基本相同的电压，并且它们的栅极电压在背驱动和5V容限模式下与它们各自的漏极基本相同的电压。还提供电路以增加级联的NMOS下拉驱动器晶体管中的一个的栅极电压，使得晶体管的漏极 - 源极结电压和栅极氧化物电压将小于后驱动时的击穿电压，并且 5 V容限模式。

9. 发明授权

US06724595B1 Output driver with over voltage protection 有权
标题翻译：具有过压保护功能的输出驱动器
公开(公告)号：US06724595B1
公开(公告)日：2004-04-20
申请号：US09790913
申请日：2001-02-22
申请人： Khusrow Kiani
发明人： Khusrow Kiani
IPC分类号： H02H320
CPC分类号： H03K19/00315
摘要： An output driver obtains over voltage protection by utilizing a first transistor to pass signals from an internal node to an external node when the driver is transmitting data, and to isolate the internal node from the external node when the driver has stopped transmitting data. When the driver has stopped transmitting data, the voltage on the external node is subject to rising. The output driver also utilizes a second transistor and a resistance to ground to control the first transistor.
摘要翻译：输出驱动器通过利用第一晶体管在驱动器正在发送数据时将信号从内部节点传递到外部节点，并在驱动器停止发送数据时将内部节点与外部节点隔离，从而获得过电压保护。当驱动程序停止发送数据时，外部节点上的电压会上升。输出驱动器还利用第二晶体管和对地电阻来控制第一晶体管。

10. 发明授权

US07397296B1 Power supply detection circuit biased by multiple power supply voltages for controlling a signal driver circuit 有权
标题翻译：电源检测电路被多个电源电压偏置，用于控制信号驱动电路
公开(公告)号：US07397296B1
公开(公告)日：2008-07-08
申请号：US11609690
申请日：2006-12-12
申请人： Khusrow Kiani
发明人： Khusrow Kiani
IPC分类号： H03L5/00
CPC分类号： H03K19/0016
摘要： A power supply detection circuit biased by at least two power supply voltages for controlling a signal driver circuit. Upstream and downstream amplifiers, powered by upstream and downstream power supply voltages, respectively, process an original control signal to produce a differential signal via output signal electrodes. Capacitances coupling respective ones of the output signal electrodes to the downstream power supply voltage and the circuit reference potential discharge and charge respective ones of the output signal electrodes in relation to initial receptions of the upstream and downstream power supply voltages and original control signal, following which voltage clamp circuitry maintains such discharged and charged states pending reception of the original control signal in a predetermined state.
摘要翻译：电源检测电路由至少两个电源电压偏置来控制信号驱动电路。上游和下游放大器分别由上游和下游电源电压供电，处理原始控制信号，以通过输出信号电极产生差分信号。将相应的输出信号电极耦合到下游电源电压和电路参考电位放电的电容，并且相对于上游和下游电源电压和原始控制信号的初始接收对相应的输出信号电极充电，随后电压钳位电路在预定状态下接收原始控制信号，保持这种放电和充电状态。

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