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1. 发明授权

US5200920A Method for programming programmable elements in programmable devices 失效
标题翻译：在可编程器件中编程可编程元件的方法
公开(公告)号：US5200920A
公开(公告)日：1993-04-06
申请号：US759944
申请日：1991-09-17
申请人： Kevin A. Norman , James D. Sansbury , Alan L. Herrmann , Matthew C. Hendricks , Behzad Nouban
发明人： Kevin A. Norman , James D. Sansbury , Alan L. Herrmann , Matthew C. Hendricks , Behzad Nouban
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454
摘要： A method for programming programmable EPROM elements in programmable logic arrays. Multiple programming passes are made through the array, with the programming pulses decreasing in duration on each pass.
摘要翻译：用于在可编程逻辑阵列中编程可编程EPROM元件的方法。通过阵列进行多个编程遍历，编程脉冲在每次通过时持续时间减少。

2. 发明授权

US06460148B2 Enhanced embedded logic analyzer 有权
公开(公告)号：US06460148B2
公开(公告)日：2002-10-01
申请号：US09887918
申请日：2001-06-21
申请人： Kerry Veenstra , Krishna Rangasayee , Alan L. Herrmann
发明人： Kerry Veenstra , Krishna Rangasayee , Alan L. Herrmann
IPC分类号： G06F1125
CPC分类号： G01R31/3177 , G01R31/318516 , G06F11/25 , G06F11/27 , G06F11/3636 , G06F11/3656 , G06F17/5027
摘要： Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint. The EDA tool directs the logic analyzer to unload the data from its capture buffer for display on a computer. The breakpoint and sample number can be changed without recompiling. A JTAG port controls the logic analyzer. Inputs and outputs of the logic analyzer are routed to unbonded JTAG-enabled I/O cells. Alternatively, a user-implemented test data register provides a JTAG-like chain of logic elements through which control and output information is shifted. Stimulus cells provide control information to the logic analyzer, and sense cells retrieve data from the logic analyzer.

3. 发明授权

US06182247B2 Embedded logic analyzer for a programmable logic device 失效
标题翻译：用于可编程逻辑器件的嵌入式逻辑分析仪
公开(公告)号：US06182247B2
公开(公告)日：2001-01-30
申请号：US08958435
申请日：1997-10-27
申请人： Alan L. Herrmann , Greg P. Nugent
发明人： Alan L. Herrmann , Greg P. Nugent
IPC分类号： G06F1750
CPC分类号： G06F8/60 , G01R31/3177 , G01R31/318516 , G06F8/65 , G06F8/71 , G06F11/0748 , G06F11/2294 , G06F17/5022 , G06F17/5027 , G06F17/5045 , G06F17/5054 , G06F2217/04 , G06Q10/06 , G06Q10/10 , Y10S707/99953 , Y10S707/99954
摘要： A technique for embedding a logic analyzer in a programmable logic device allows debugging of such a device in its actual operating conditions. A logic analyzer circuit is embedded within a PLD, it captures and stores logic signals, and it unloads these signals through an interface to be viewed on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, specifies the number of samples to be stored, and specifies a system clock signal and a trigger condition that will begin the acquisition of data. The EDA tool then automatically inserts the logic analyzer circuit into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool communicates with the embedded logic analyzer in order to arm the circuit and to poll it until an acquisition has been made. The EDA tool then directs the logic analyzer to unload the data from its capture buffer and then displays the data on the computer. The logic analyzer circuit may then be rearmed to capture another sequence of sample values. The trigger condition may be changed without recompiling. The design may be recompiled with new logic analyzer parameters to debug a different portion.
摘要翻译：在可编程逻辑器件中嵌入逻辑分析仪的技术允许在其实际操作条件下调试这种器件。逻辑分析仪电路嵌入在PLD中，它捕获并存储逻辑信号，并通过接口卸载这些信号，以便在计算机上查看。使用在计算机系统上运行的电子设计自动化（EDA）软件工具，工程师指定要监视的PLD的信号，指定要存储的采样数量，并指定将开始的系统时钟信号和触发条件获取数据。然后，EDA工具自动将逻辑分析仪电路插入到PLD的电子设计中，PLD的编译和下载以配置PLD。使用连接在PLD和计算机之间的接口，EDA工具与嵌入式逻辑分析仪通信，以便对电路进行轮询并进行轮询，直到采集完成。然后，EDA工具指示逻辑分析仪从其捕获缓冲区卸载数据，然后在计算机上显示数据。然后逻辑分析器电路可以被重新调制以捕获另一个采样值序列。可以更改触发条件，无需重新编译。可以使用新的逻辑分析仪参数重新编译设计，以调试不同的部分。

4. 发明授权

US6026226A Local compilation in context within a design hierarchy 失效
标题翻译：在设计层次结构中的上下文中的本地编译
公开(公告)号：US6026226A
公开(公告)日：2000-02-15
申请号：US958798
申请日：1997-10-27
申请人： Francis B. Heile , Tamlyn V. Rawls , Alan L. Herrmann , Brent A. Fairbanks , David Karchmer
发明人： Francis B. Heile , Tamlyn V. Rawls , Alan L. Herrmann , Brent A. Fairbanks , David Karchmer
IPC分类号： G01R31/317 , G01R31/3177 , G01R31/3185 , G06F9/44 , G06F9/445 , G06F11/14 , G06F11/273 , G06F11/28 , G06F12/00 , G06F17/50 , G06Q10/06 , G06Q10/10 , H01L21/82
CPC分类号： G06F8/60 , G01R31/3177 , G01R31/318516 , G06F11/0748 , G06F11/2294 , G06F17/5022 , G06F17/5027 , G06F17/5045 , G06F17/5054 , G06F8/65 , G06F8/71 , G06Q10/06 , G06Q10/10 , G06F2217/04 , Y10S707/99953 , Y10S707/99954
摘要： A technique for allowing local compilation at any level within a design hierarchy tree for a programmable logic device allows a user to compile within the context of the entire design using inherited parameter values and assignments from any parent nodes within the design hierarchy tree. A user is allowed to perform an isolated, local compilation that gives a compilation result as if the lower level node had been compiled within the context of the complete design. This local compilation is performed even though assignments, parameters, and logic options of parent nodes have not been compiled. An "action point" is specified at a node where a local compilation, timing analysis or simulation is to occur. A method compiles design source files that represent a PLD design. The design source files specify design entities that are represented as nodes in a design hierarchy tree. A first step analyzes the design source files to determine what design entities are represented in the source files. Starting from the root node down to the action point, the following steps are performed at each node: resolving current assignments based upon higher assignments at nodes located between the current node and the root node of said hierarchy tree, and elaborating the current node to produce a netlist. Once the action point node has been reached, then lower nodes of the hierarchy tree below the action point are elaborated down to the leaf nodes to produce a netlist for each of these lower nodes.
摘要翻译：允许在可编程逻辑设备的设计层次结构树内的任何级别进行本地编译的技术允许用户使用继承的参数值和在设计层级树内的任何父节点的分配在整个设计的上下文中进行编译。允许用户执行一个孤立的本地编译，给出一个编译结果，就好像在完整设计的上下文中编译了较低级节点一样。即使尚未编译父节点的分配，参数和逻辑选项，也会执行本地编译。在要进行本地编译，定时分析或模拟的节点处指定“动作点”。一种方法编译表示PLD设计的设计源文件。设计源文件指定在设计层次结构树中表示为节点的设计实体。第一步分析设计源文件以确定哪些设计实体在源文件中被表示。从根节点到动作点，在每个节点执行以下步骤：基于位于当前节点和所述层次树的根节点之间的节点处的较高分配来解析当前分配，并且详细描述当前节点产生网表。一旦达到了动作点节点，则动作点下方的层次结构树的下层节点被细化到叶节点，以产生这些下层节点中的每一个的网表。

5. 发明授权

US06704889B2 Enhanced embedded logic analyzer 有权
标题翻译：增强型嵌入式逻辑分析仪
公开(公告)号：US06704889B2
公开(公告)日：2004-03-09
申请号：US10212839
申请日：2002-08-06
申请人： Kerry Veenstra , Krishna Rangasayee , Alan L. Herrmann
发明人： Kerry Veenstra , Krishna Rangasayee , Alan L. Herrmann
IPC分类号： G06F1125
CPC分类号： G01R31/3177 , G01R31/318516 , G06F11/25 , G06F11/27 , G06F11/3636 , G06F11/3656 , G06F17/5027
摘要： Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint. The EDA tool directs the logic analyzer to unload the data from its capture buffer for display on a computer. The breakpoint and sample number can be changed without recompiling. A JTAG port controls the logic analyzer. Inputs and outputs of the logic analyzer are routed to unbonded JTAG-enabled I/O cells. Alternatively, a user-implemented test data register provides a JTAG-like chain of logic elements through which control and output information is shifted. Stimulus cells provide control information to the logic analyzer, and sense cells retrieve data from the logic analyzer.
摘要翻译：在可编程逻辑器件中嵌入逻辑分析仪可以在触发条件（断点）之前和之后捕获信号。嵌入在PLD中的逻辑分析仪捕获并存储逻辑信号。它会卸载这些信号，以便在计算机上查看。使用在计算机系统上运行的电子设计自动化（EDA）软件工具，工程师指定要监视的PLD的信号，断点，要存储的样本总数，断点发生后要捕获的样本数，以及系统时钟信号。 EDA工具自动将逻辑分析仪插入PLD的电子设计中，PLD的编译和下载以配置PLD。使用连接在PLD和计算机之间的接口，EDA工具命令嵌入式逻辑分析仪运行。信号在环形缓冲RAM存储器中运行时连续存储。一旦发生断点，除了在断点之前捕获的信号之外，如果需要，还会捕获更多的采样。 EDA工具指示逻辑分析仪从其捕获缓冲区卸载数据，以便在计算机上显示。可以更改断点和样本编号，无需重新编译。 JTAG端口控制逻辑分析仪。逻辑分析仪的输入和输出被路由到无键JTAG的I / O单元。或者，用户实现的测试数据寄存器提供了类似JTAG的逻辑元件链，控制和输出信息通过该逻辑元件被移位。激励单元向逻辑分析仪提供控制信息，并且感测单元从逻辑分析仪检索数据。

6. 发明授权

US06408432B1 Apparatus and method for in-system programming of integrated circuits containing programmable elements 有权
标题翻译：包含可编程元件的集成电路的系统编程的装置和方法
公开(公告)号：US06408432B1
公开(公告)日：2002-06-18
申请号：US09552575
申请日：2000-04-19
申请人： Alan L. Herrmann , Timothy J. Southgate
发明人： Alan L. Herrmann , Timothy J. Southgate
IPC分类号： G06F945
CPC分类号： G06F17/5054
摘要： An apparatus and method for in-system programming of programmable devices includes a device configuration program with adaptive programming source code instructions that characterize device configuration instructions and data. The adaptive source code instructions may include conditional branches, subroutines, variables, configurable arrays, integer operators, and Boolean operators. These features allow for more compact and efficient device configuration instructions and data. An interpreter converts the device configuration program into formatted device configuration instructions and data. The formatted device configuration instructions and data are preferably compatible with IEEE 1149.1 JTAG-BST specifications. The formatted device configuration instructions and data are used to program a programmable device in the manner specified by the adaptive programming source code instructions.
摘要翻译：用于可编程器件的系统内编程的装置和方法包括具有表征器件配置指令和数据的自适应编程源代码指令的器件配置程序。自适应源代码指令可以包括条件分支，子程序，变量，可配置数组，整数运算符和布尔运算符。这些功能允许更紧凑和高效的设备配置指令和数据。解释器将设备配置程序转换为格式化的设备配置指令和数据。格式化的设备配置指令和数据优选地符合IEEE 1149.1 JTAG-BST规范。格式化的设备配置指令和数据用于以自适应编程源代码指令指定的方式对可编程设备进行编程。

7. 发明授权

US06389558B1 Embedded logic analyzer for a programmable logic device 有权
标题翻译：用于可编程逻辑器件的嵌入式逻辑分析仪
公开(公告)号：US06389558B1
公开(公告)日：2002-05-14
申请号：US09610787
申请日：2000-07-06
申请人： Alan L. Herrmann , Greg P. Nugent
发明人： Alan L. Herrmann , Greg P. Nugent
IPC分类号： G06F1750
CPC分类号： G06F8/60 , G01R31/3177 , G01R31/318516 , G06F8/65 , G06F8/71 , G06F11/0748 , G06F11/2294 , G06F17/5022 , G06F17/5027 , G06F17/5045 , G06F17/5054 , G06F2217/04 , G06Q10/06 , G06Q10/10 , Y10S707/99953 , Y10S707/99954
摘要： A technique for embedding a logic analyzer in a programmable logic device allows debugging of such a device in its actual operating conditions. A logic analyzer circuit is embedded within a PLD, it captures and stores logic signals, and it unloads these signals through an interface to be viewed on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, specifies the number of samples to be stored, and specifies a system clock signal and a trigger condition that will begin the acquisition of data. The EDA tool then automatically inserts the logic analyzer circuit into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool communicates with the embedded logic analyzer in order to arm the circuit and to poll it until an acquisition has been made. The EDA tool then directs the logic analyzer to unload the data from its capture buffer and then displays the data on the computer. The logic analyzer circuit may then be rearmed to capture another sequence of sample values. The trigger condition may be changed without recompiling. The design may be recompiled with new logic analyzer parameters to debug a different portion.
摘要翻译：在可编程逻辑器件中嵌入逻辑分析仪的技术允许在其实际操作条件下调试这种器件。逻辑分析仪电路嵌入在PLD中，它捕获并存储逻辑信号，并通过接口卸载这些信号，以便在计算机上查看。使用在计算机系统上运行的电子设计自动化（EDA）软件工具，工程师指定要监视的PLD的信号，指定要存储的采样数量，并指定将开始的系统时钟信号和触发条件获取数据。然后，EDA工具自动将逻辑分析仪电路插入到PLD的电子设计中，PLD的编译和下载以配置PLD。使用连接在PLD和计算机之间的接口，EDA工具与嵌入式逻辑分析仪通信，以便对电路进行轮询并进行轮询，直到采集完成。然后，EDA工具指示逻辑分析仪从其捕获缓冲区卸载数据，然后在计算机上显示数据。然后逻辑分析器电路可以被重新调制以捕获另一个采样值序列。可以更改触发条件，无需重新编译。可以使用新的逻辑分析仪参数重新编译设计，以调试不同的部分。

8. 发明授权

US06286114B1 Enhanced embedded logic analyzer 有权
标题翻译：增强型嵌入式逻辑分析仪
公开(公告)号：US06286114B1
公开(公告)日：2001-09-04
申请号：US09186607
申请日：1998-11-06
申请人： Kerry Veenstra , Krishna Rangasayee , Alan L. Herrmann
发明人： Kerry Veenstra , Krishna Rangasayee , Alan L. Herrmann
IPC分类号： G06F1125
CPC分类号： G01R31/3177 , G01R31/318516 , G06F11/25 , G06F11/27 , G06F11/3636 , G06F11/3656 , G06F17/5027
摘要： Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint. The EDA tool directs the logic analyzer to unload the data from its capture buffer for display on a computer. The breakpoint and sample number can be changed without recompiling. A JTAG port controls the logic analyzer. Inputs and outputs of the logic analyzer are routed to unbonded JTAG-enabled I/O cells. Alternatively, a user-implemented test data register provides a JTAG-like chain of logic elements through which control and output information is shifted. Stimulus cells provide control information to the logic analyzer, and sense cells retrieve data from the logic analyzer.
摘要翻译：在可编程逻辑器件中嵌入逻辑分析仪可以在触发条件（断点）之前和之后捕获信号。嵌入在PLD中的逻辑分析仪捕获并存储逻辑信号。它会卸载这些信号，以便在计算机上查看。使用在计算机系统上运行的电子设计自动化（EDA）软件工具，工程师指定要监视的PLD的信号，断点，要存储的样本总数，断点发生后要捕获的样本数，以及系统时钟信号。 EDA工具自动将逻辑分析仪插入PLD的电子设计中，PLD的编译和下载以配置PLD。使用连接在PLD和计算机之间的接口，EDA工具命令嵌入式逻辑分析仪运行。信号在环形缓冲RAM存储器中运行时连续存储。一旦发生断点，除了在断点之前捕获的信号之外，如果需要，还会捕获更多的采样。 EDA工具指示逻辑分析仪从其捕获缓冲区卸载数据，以便在计算机上显示。可以更改断点和样本编号，无需重新编译。 JTAG端口控制逻辑分析仪。逻辑分析仪的输入和输出被路由到无键JTAG的I / O单元。或者，用户实现的测试数据寄存器提供了类似JTAG的逻辑元件链，控制和输出信息通过该逻辑元件被移位。激励单元向逻辑分析仪提供控制信息，并且感测单元从逻辑分析仪检索数据。

9. 发明授权

US06247147B1 Enhanced embedded logic analyzer 有权
公开(公告)号：US06247147B1
公开(公告)日：2001-06-12
申请号：US09186608
申请日：1998-11-06
申请人： Kerry Beenstra , Krishna Rangasayee , Alan L. Herrmann
发明人： Kerry Beenstra , Krishna Rangasayee , Alan L. Herrmann
IPC分类号： G01R3128
CPC分类号： G01R31/3177 , G01R31/318516 , G06F17/5027
摘要： Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint. The EDA tool directs the logic analyzer to unload the data from its capture buffer for display on a computer. The breakpoint and sample number can be changed without recompiling. A JTAG port controls the logic analyzer. Inputs and outputs of the logic analyzer are routed to unbonded JTAG-enabled I/O cells. Alternatively, a user-implemented test data register provides a JTAG-like chain of logic elements through which control and output information is shifted. Stimulus cells provide control information to the logic analyzer, and sense cells retrieve data from the logic analyzer.

10. 发明授权

US6134707A Apparatus and method for in-system programming of integrated circuits containing programmable elements 失效
公开(公告)号：US6134707A
公开(公告)日：2000-10-17
申请号：US872652
申请日：1997-06-10
申请人： Alan L. Herrmann , Timothy J. Southgate
发明人： Alan L. Herrmann , Timothy J. Southgate
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： G06F17/5054
摘要： An apparatus and method for in-system programming of programmable devices includes a device configuration program with adaptive programming source code instructions that characterize device configuration instructions and data. The adaptive source code instructions may include conditional branches, subroutines, variables, configurable arrays, integer operators, and Boolean operators. These features allow for more compact and efficient device configuration instructions and data. An interpreter converts the device configuration program into formatted device configuration instructions and data. The formatted device configuration instructions and data are preferably compatible with IEEE 1149.1 JTAG-BST specifications. The formatted device configuration instructions and data are used to program a programmable device in the manner specified by the adaptive programming source code instructions.

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