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1. 发明授权

US06384437B1 Low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer 失效
标题翻译：在绝缘层上使用选择性硅外延生长（SEG）的低泄漏DRAM结构
公开(公告)号：US06384437B1
公开(公告)日：2002-05-07
申请号：US09963411
申请日：2001-09-27
申请人： Kheng Chok Tee , Randall Cher Liang Cha , Lap Chan
发明人： Kheng Chok Tee , Randall Cher Liang Cha , Lap Chan
IPC分类号： H01L27148
CPC分类号： H01L27/10873 , H01L27/10808
摘要： Low current leakage DRAM structures are achieved using a selective silicon epitaxial growth over an insulating layer on memory cell (device) areas. An insulating layer, that also serves as a stress-release layer, and a Si3N4 hard mask are patterned to leave portions over the memory cell areas. Shallow trenches are etched in the substrate and filled with a CVD oxide which is polished back to the hard mask to form shallow trench isolation (STI) around the memory cell areas. The hard mask is selectively removed to form recesses in the STI aligned over the memory cell areas exposing the underlying insulating layer. Openings are etched in the insulating layer to provide a silicon-seed surface from which is grown a selective epitaxial layer extending over the insulating layer within the recesses. After growing a gate oxide on the epitaxial layer, FETs and DRAM capacitors can be formed on the epitaxial layer. The insulating layer under the epitaxial layer drastically reduces the capacitor leakage current and improves DRAM device performance. This self-aligning method also increases memory cell density, and is integratable into current DRAM processes to reduce cost.
摘要翻译：使用在存储器单元（器件）区域上的绝缘层上的选择性硅外延生长来实现低电流泄漏DRAM结构。也用作应力释放层的绝缘层和Si 3 N 4硬掩模被图案化以在存储器单元区域上留下部分。在衬底中蚀刻浅沟槽，并填充有CVD氧化物，其被抛光回硬掩模以在存储器单元区域周围形成浅沟槽隔离（STI）。选择性地去除硬掩模，以在STI暴露下面的绝缘层的存储单元区域上对准STI中形成凹槽。在绝缘层中蚀刻开口以提供硅种子表面，从该晶种表面生长在凹陷内的绝缘层上延伸的选择性外延层。在外延层上生长栅极氧化物之后，可以在外延层上形成FET和DRAM电容器。外延层下方的绝缘层大大降低了电容器的漏电流，提高了DRAM器件性能。这种自对准方法也增加了存储单元密度，并且可以集成到当前的DRAM工艺中以降低成本。

2. 发明授权

US06319772B1 Method for making low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer 失效
标题翻译：在绝缘层上制造使用选择性硅外延生长（SEG）的低泄漏DRAM结构的方法
公开(公告)号：US06319772B1
公开(公告)日：2001-11-20
申请号：US09697946
申请日：2000-10-30
申请人： Kheng Chok Tee , Randall Cher Liang Cha , Lap Chan
发明人： Kheng Chok Tee , Randall Cher Liang Cha , Lap Chan
IPC分类号： H01L218242
CPC分类号： H01L27/10873 , H01L27/10808
摘要： Low current leakage DRAM structures are achieved using a selective silicon epitaxial growth over an insulating layer on memory cell (device) areas. An insulating layer, that also serves as a stress-release layer, and a Si3N4 hard mask are patterned to leave portions over the memory cell areas. Shallow trenches are etched in the substrate and filled with a CVD oxide which is polished back to the hard mask to form shallow trench isolation (STI) around the memory cell areas. The hard mask is selectively removed to form recesses in the STI aligned over the memory cell areas exposing the underlying insulating layer. Openings are etched in the insulating layer to provide a silicon-seed surface from which is grown a selective epitaxial layer extending over the insulating layer within the recesses. After growing a gate oxide on the epitaxial layer, FETs and DRAM capacitors can be formed on the epitaxial layer. The insulating layer under the epitaxial layer drastically reduces the capacitor leakage current and improves DRAM device performance. This self-aligning method also increases memory cell density, and is integratable into current DRAM processes to reduce cost.
摘要翻译：使用在存储器单元（器件）区域上的绝缘层上的选择性硅外延生长来实现低电流泄漏DRAM结构。也用作应力释放层的绝缘层和Si 3 N 4硬掩模被图案化以在存储器单元区域上留下部分。在衬底中蚀刻浅沟槽，并填充有CVD氧化物，其被抛光回硬掩模以在存储器单元区域周围形成浅沟槽隔离（STI）。选择性地去除硬掩模，以在STI暴露下面的绝缘层的存储单元区域上对准STI中形成凹槽。在绝缘层中蚀刻开口以提供硅种子表面，从该晶种表面生长在凹陷内的绝缘层上延伸的选择性外延层。在外延层上生长栅极氧化物之后，可以在外延层上形成FET和DRAM电容器。外延层下方的绝缘层大大降低了电容器的漏电流，提高了DRAM器件性能。这种自对准方法也增加了存储单元密度，并且可以集成到当前的DRAM工艺中以降低成本。

3. 发明授权

US06319767B1 Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique 有权
标题翻译：用于通过等离子体灰化和硬掩蔽技术消除MIM电容器底金属图案化期间的顶部金属角成形的方法
公开(公告)号：US06319767B1
公开(公告)日：2001-11-20
申请号：US09798639
申请日：2001-03-05
申请人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
发明人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/31122 , H01L21/31144 , H01L21/32136 , H01L21/32139
摘要： A method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is described. An insulating layer is provided overlying a semiconductor substrate. A composite metal stack is formed comprising a first metal layer overlying the insulating layer, a capacitor dielectric layer overlying the first metal layer, a second metal layer overlying the capacitor dielectric layer, and a hard mask layer overlying the second metal layer. A first photoresist mask is formed overlying the hard mask layer. The composite metal stack is patterned using the first photoresist mask as an etching mask whereby the patterned first metal layer forms a bottom electrode of the capacitor. A portion of the first photoresist mask is removed by plasma ashing to form a second photoresist mask narrower than the first photoresist mask. The hard mask layer is patterned using the second photoresist mask as an etching mask. The second metal layer is patterned using the hard mask layer as an etching mask whereby the second metal layer forms a top electrode of the capacitor to complete fabrication of a metal-insulator-metal capacitor.
摘要翻译：描述了一种用于制造金属 - 绝缘体 - 金属电容器的方法，其中消除了图案化期间的顶部金属角成形。绝缘层设置在半导体衬底上。形成复合金属堆叠，其包括覆盖绝缘层的第一金属层，覆盖第一金属层的电容器电介质层，覆盖电容器电介质层的第二金属层和覆盖第二金属层的硬掩模层。第一光致抗蚀剂掩模形成在硬掩模层上。使用第一光致抗蚀剂掩模将复合金属堆叠图案化为蚀刻掩模，由此图案化的第一金属层形成电容器的底部电极。通过等离子体灰化除去第一光致抗蚀剂掩模的一部分，以形成比第一光致抗蚀剂掩模窄的第二光刻胶掩模。使用第二光致抗蚀剂掩模将硬掩模层图案化为蚀刻掩模。使用硬掩模层作为蚀刻掩模对第二金属层进行构图，由此第二金属层形成电容器的顶部电极，以完成金属 - 绝缘体 - 金属电容器的制造。

4. 发明授权

US06284610B1 Method to reduce compressive stress in the silicon substrate during silicidation 失效
标题翻译：降低硅衬底中压缩应力的方法
公开(公告)号：US06284610B1
公开(公告)日：2001-09-04
申请号：US09666315
申请日：2000-09-21
申请人： Randall Cher Liang Cha , Chee Tee Chua , Kin Leong Pey , Lap Chan
发明人： Randall Cher Liang Cha , Chee Tee Chua , Kin Leong Pey , Lap Chan
IPC分类号： H01L21336
CPC分类号： H01L29/66628 , H01L29/41775 , H01L29/41783 , H01L29/665 , H01L29/7845
摘要： A method for siliciding source/drain junctions is described wherein compressive stress of the underlying silicon is avoided by the insertion of a buffer layer between the silicide and the silicon. A gate electrode and associated source/drain extensions are provided in and on a semiconductor substrate. A buffer oxide layer is deposited overlying the semiconductor substrate and the gate electrode. A polysilicon layer is deposited overlying the buffer oxide layer. The polysilicon layer will form the source/drain junctions and silicon source. The source/drain junctions are silicided whereby the buffer oxide layer provides compressive stress relief during the siliciding.
摘要翻译：描述了用于硅化源极/漏极结的方法，其中通过在硅化物和硅之间插入缓冲层来避免下面的硅的压缩应力。栅极电极和相关的源极/漏极延伸部设置在半导体衬底中和半导体衬底上。沉积在半导体衬底和栅电极上的缓冲氧化层。堆叠在缓冲氧化物层上的多晶硅层。多晶硅层将形成源极/漏极结和硅源。源极/漏极结是硅化的，由此缓冲氧化物层在硅化期间提供压缩应力释放。

5. 发明授权

US06355563B1 Versatile copper-wiring layout design with low-k dielectric integration 失效
标题翻译：多功能铜线布局设计，低k电介质集成
公开(公告)号：US06355563B1
公开(公告)日：2002-03-12
申请号：US09798652
申请日：2001-03-05
申请人： Randall Cher Liang Cha , Alex See , Yeow Kheng Lim , Tae Jong Lee , Lap Chan
发明人： Randall Cher Liang Cha , Alex See , Yeow Kheng Lim , Tae Jong Lee , Lap Chan
IPC分类号： H01L2144
CPC分类号： H01L21/76802 , H01L21/76825 , H01L21/76831 , H01L21/76832
摘要： A method to integrate low dielectric constant dielectric materials with copper metallization is described. A metal line is provided overlying a semiconductor substrate and having a nitride capping layer thereover. A polysilicon layer is deposited over the nitride layer and patterned to form dummy vias. A dielectric liner layer is conformally deposited overlying the nitride layer and dummy vias. A dielectric layer having a low dielectric constant is spun-on overlying the liner layer and covering the dummy vias. The dielectric layer is polished down whereby the dummy vias are exposed. Thereafter, the dielectric layer is cured whereby a cross-linked surface layer is formed. The dummy vias are removed thereby exposing a portion of the nitride layer within the via openings. The exposed nitride layer is removed. The via openings are filled with a copper layer which is planarized to complete copper metallization in the fabrication of an integrated circuit device.
摘要翻译：描述了一种将低介电常数电介质材料与铜金属化相结合的方法。金属线设置在半导体衬底上并且在其上具有氮化物覆盖层。多晶硅层沉积在氮化物层上并被图案化以形成虚拟通孔。电介质衬垫层共形沉积在氮化物层和虚拟通孔之上。将具有低介电常数的介电层旋涂在衬层上并覆盖虚拟通孔。抛光电介质层，从而暴露虚拟通孔。此后，电介质层被固化，由此形成交联表面层。去除虚设通孔，从而将通孔的一部分氮化物层露出。去除暴露的氮化物层。通孔开口填充有铜层，该铜层在集成电路器件的制造中被平坦化以完成铜金属化。

6. 发明授权

US06348385B1 Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant 有权
标题翻译：使用具有低介电常数的原位掺杂间隔物的具有小覆盖电容的短沟道CMOS晶体管的方法
公开(公告)号：US06348385B1
公开(公告)日：2002-02-19
申请号：US09726256
申请日：2000-11-30
申请人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Chee Tee Chua
发明人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Chee Tee Chua
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/2255 , H01L21/28167 , H01L29/4983 , H01L29/51 , H01L29/66537 , H01L29/66553 , H01L29/7834
摘要： The method for a transistor using a replacement gate process that has a doped low-K dielectric spacer that lowers the junction capacitance. A dummy gate is formed over a substrate. Ions are implanted into the substrate using the dummy gate as an implant mask to form source and drain regions. A masking layer is formed on the substrate over the source and drain regions. We remove the dummy gate. Doped low k spacers are formed on the sidewalls of the masking layer. The doped spacers are heated to diffuse dopant into the substrate to form lightly doped drain (LDD regions). We form a high k gate dielectric layer over the masking layer. A gate layer is formed over the high K dielectric layer. The gate layer is chemical-mechanical polished (CMP) to form a gate over the high k dielectric layer and to remove the gate layer over the masking layer.
摘要翻译：使用具有降低结电容的掺杂低K电介质间隔物的替代栅极工艺的晶体管的方法。在基板上形成虚拟栅极。使用伪栅极作为注入掩模将离子注入到衬底中以形成源区和漏区。在源极和漏极区上的衬底上形成掩模层。我们删除虚拟门。在掩蔽层的侧壁上形成掺杂的低k间隔物。掺杂的间隔物被加热以将掺杂剂扩散到衬底中以形成轻掺杂漏极（LDD区）。我们在掩模层上形成一个高k栅介质层。在高K电介质层上形成栅极层。栅极层是化学机械抛光（CMP），以在高k电介质层上形成栅极，并且去除掩模层上的栅极层。

7. 发明授权

US06878623B2 Technique to achieve thick silicide film for ultra-shallow junctions 失效
标题翻译：实现超浅结的厚硅化物薄膜技术
公开(公告)号：US06878623B2
公开(公告)日：2005-04-12
申请号：US10457885
申请日：2003-06-09
申请人： Cheng Cheh Tan , Randall Cher Liang Cha , Alex See , Lap Chan
发明人： Cheng Cheh Tan , Randall Cher Liang Cha , Alex See , Lap Chan
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L29/66507 , H01L29/41783 , H01L29/665 , H01L29/6656
摘要： A gate structure having associated (LDD) regions and source and drain is formed as is conventional. A first oxide spacer, for example, is formed along the sidewalls of the gate structure. A layer of metal such as titanium is then deposited over the surface of the gate structure. Second sidewall spacers are formed covering the metal over the first sidewall spacer and covering the metal over isolation regions. A layer of polysilicon is deposited over the surface of the gate structure. A rapid thermal annealing (RTA) is performed causing the metal to react with both the silicon in the junction below the metal and the polysilicon above the metal forming a metal silicide. Metal along the sidewalls between the first and second sidewall spacers and over the isolation regions does not react and is etched away. By providing an additional source of silicon in the polysilicon layer above the metal, a thicker silicide is achieved.
摘要翻译：具有相关联（LDD）区域和源极和漏极的栅极结构如常规形成。例如，沿着栅极结构的侧壁形成第一氧化物间隔物。然后在栅极结构的表面上沉积诸如钛的金属层。形成第二侧壁间隔物，覆盖第一侧壁间隔物上的金属，并将金属覆盖在隔离区上。在栅极结构的表面上沉积多晶硅层。进行快速热退火（RTA），使得金属与金属之下的结中的硅和形成金属硅化物的金属上方的多晶硅反应。沿着第一和第二侧壁间隔物之间的侧壁以及隔离区域上的金属不会反应并被蚀刻掉。通过在金属上方的多晶硅层中提供附加的硅源，可获得更厚的硅化物。

8. 发明授权

US06432797B1 Simplified method to reduce or eliminate STI oxide divots 失效
标题翻译：简化方法来减少或消除STI氧化层
公开(公告)号：US06432797B1
公开(公告)日：2002-08-13
申请号：US09768487
申请日：2001-01-25
申请人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
发明人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
IPC分类号： H01L2176
CPC分类号： H01L21/76237 , H01L21/31053 , H01L21/31055
摘要： A method for forming shallow trench isolation wherein oxide divots at the edge of the isolation and active regions are reduced or eliminated is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. Nitrogen atoms are implanted into the oxide layer overlying the trench. The substrate is annealed whereby a layer of nitrogen-rich oxide is formed at the surface of the oxide layer overlying the trench. The oxide layer is planarized to the semiconductor substrate wherein the nitrogen-rich oxide layer is planarized more slowly than the oxide layer resulting in a portion of the oxide layer remaining overlying the trench after the oxide layer overlying the semiconductor substrate has been removed wherein the portion of the oxide layer remaining provides a smooth transition between the shallow trench isolation and the active areas completing the formation of shallow trench isolation in the fabrication of an integrated circuit device.
摘要翻译：描述了形成浅沟槽隔离的方法，其中在隔离和有源区的边缘处的氧化物凹陷被减少或消除。将沟槽蚀刻到半导体衬底中。沉积在半导体衬底上并填充沟槽的氧化物层。将氮原子注入到覆盖沟槽的氧化物层中。将衬底退火，由此在覆盖沟槽的氧化物层的表面上形成一层富氮氧化物。氧化物层平坦化到半导体衬底，其中富氧氧化物层平坦化比氧化物层缓慢，导致一部分氧化物层保留在沟槽上方，在氧化物层覆盖半导体衬底之后，其中部分剩余的氧化物层在浅沟槽隔离和有源区域之间提供平滑的过渡，从而在集成电路器件的制造中完成浅沟槽隔离的形成。

9. 发明授权

US06387784B1 Method to reduce polysilicon depletion in MOS transistors 失效
标题翻译：减少MOS晶体管多晶硅耗尽的方法
公开(公告)号：US06387784B1
公开(公告)日：2002-05-14
申请号：US09810121
申请日：2001-03-19
申请人： Yung Fu Chong , Randall Cher Liang Cha , Lap Chan , Kin Leong Pey
发明人： Yung Fu Chong , Randall Cher Liang Cha , Lap Chan , Kin Leong Pey
IPC分类号： H01L214763
CPC分类号： H01L29/6656 , H01L21/76886
摘要： A method is provided to reduce poly depletion in MOS transistors. Conventionally, after a polysilicon electrode has been doped, an anneal step is usually performed to activate the dopants. However, the anneal step may be insufficient to drive the implanted impurities down the entire depth of the polysilicon electrode. Consequently, a portion of the polysilicon gate nearest to the gate oxide will be depleted of dopants. This poly depletion will have a detrimental effect on the control of the threshold voltage, and hence on the performance of the device. It is disclosed in the present invention a method of forming polysilicon gates where dopant depletion at the interface near the gate oxide layer is alleviated substantially by using laser annealing; however, by first pre-amorphizing the polycrystalline silicon prior to ion (implantation to a desired depth such that during laser annealing the dopants will diffuse uniformly to a melt depth. In this manner, poly depletion effect is greatly reduced and hence performance of the device improved. The disclosed method is applicable to both n+ doped polysilicon gates (NMOS) and p+ doped polysilicon gates (PMOS).
摘要翻译：提供了一种减少MOS晶体管多余耗尽的方法。通常，在掺杂多晶硅电极之后，通常进行退火步骤以激活掺杂剂。然而，退火步骤可能不足以在多晶硅电极的整个深度下驱动注入的杂质。因此，最接近栅极氧化物的多晶硅栅极的一部分将耗尽掺杂剂。这种多余耗尽将对阈值电压的控制以及因此对器件的性能具有不利影响。在本发明中公开了一种形成多晶硅栅极的方法，其中在栅极氧化物层附近的界面处的掺杂剂消耗基本上通过使用激光退火得到缓解; 然而，通过在离子之前首先将多晶硅预先失配（植入到期望的深度，使得在激光退火期间，掺杂剂将均匀地扩散到熔体深度），以这种方式，多余的效应被大大降低，因此器件的性能所公开的方法适用于n +掺杂多晶硅栅极（NMOS）和p +掺杂多晶硅栅极（PMOS）。

10. 发明授权

US06468906B1 Passivation of copper interconnect surfaces with a passivating metal layer 有权
标题翻译：用钝化金属层钝化铜互连表面
公开(公告)号：US06468906B1
公开(公告)日：2002-10-22
申请号：US09617009
申请日：2000-07-14
申请人： Lap Chan , Kuan Pei Yap , Kheng Chok Tee , Flora S. Ip , Wye Boon Loh
发明人： Lap Chan , Kuan Pei Yap , Kheng Chok Tee , Flora S. Ip , Wye Boon Loh
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/76858 , H01L21/76867 , H01L21/76886
摘要： An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.
摘要翻译：在IMD层中的互连孔中形成半导体器件上的IMD层上的互连线。互连孔在IMD层中具有壁和底部。在孔的壁和底部形成扩散阻挡层。用铜金属线填充互连孔。执行CMP步骤以使器件平坦化，并移除IMD层上方的铜。在孔的顶部包埋铜金属线的铜金属线的表面上沉积钝化金属层。或者，铜金属线层的覆盖沉积覆盖扩散层并用铜金属线填充互连孔。执行CMP工艺以平坦化器件以去除IMD层上方的铜。在自对准沉积工艺中，在孔的顶部封装铜金属线的铜金属线的表面上沉积钝化金属层。

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