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1. 发明申请

US20090217005A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR SELECTIVELY ACCELERATING EARLY INSTRUCTION PROCESSING 失效
标题翻译：方法，系统和计算机程序产品，用于选择性加速早期指导处理
公开(公告)号：US20090217005A1
公开(公告)日：2009-08-27
申请号：US12037861
申请日：2008-02-26
申请人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung K. Shum
发明人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung K. Shum
IPC分类号： G06F9/30
CPC分类号： G06F9/3826 , G06F9/3836
摘要： A method for selectively accelerating early instruction processing including receiving an instruction data that is normally processed in an execution stage of a processor pipeline, wherein a configuration of the instruction data allows a processing of the instruction data to be accelerated from the execution stage to an address generation stage that occurs earlier in the processor pipeline than the execution stage, determining whether the instruction data can be dispatched to the address generation stage to be processed without being delayed due to an unavailability of a processing resource needed for the processing of the instruction data in the address generation stage, dispatching the instruction data to be processed in the address generation stage if it can be dispatched without being delayed due to the unavailability of the processing resource, and dispatching the instruction data to be processed in the execution stage if it can not be dispatched without being delayed due to the unavailability of the processing resource, wherein the processing of the instruction data is selectively accelerated using an address generation interlock scheme. A corresponding system and computer program product.
摘要翻译：一种用于选择性地加速早期指令处理的方法，包括接收在处理器流水线的执行阶段中正常处理的指令数据，其中指令数据的配置允许指令数据的处理从执行阶段加速到地址在处理器流水线中比执行阶段更早发生的生成阶段，确定指令数据是否可以被分派到要处理的地址生成阶段，而不会由于处理指令数据所需的处理资源的不可用而被延迟地址生成阶段，如果能够由于处理资源的不可用而被分派而不被延迟，则在地址生成阶段调度要处理的指令数据，并且如果不能在执行阶段调度要处理的指令数据由于你而不被推迟处理资源的可用性，其中使用地址生成互锁方案选择性地加速指令数据的处理。相应的系统和计算机程序产品。

2. 发明申请

US20110167244A1 EARLY INSTRUCTION TEXT BASED OPERAND STORE COMPARE REJECT AVOIDANCE 失效
标题翻译：早期指导性文本操作存储比较对象避免
公开(公告)号：US20110167244A1
公开(公告)日：2011-07-07
申请号：US13050484
申请日：2011-03-17
申请人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung K. Shum
发明人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung K. Shum
IPC分类号： G06F9/30
CPC分类号： G06F9/3826 , G06F9/3016 , G06F9/382 , G06F9/3834 , G06F9/3836 , G06F9/3861
摘要： A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address information. The system also includes delay logic to monitor the instruction stream. The delay logic performs a method that includes detecting a load instruction following a store instruction in the instruction stream, comparing the operand address information of the store instruction with the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to detecting a common field value between the operand address information of the store instruction and the load instruction.
摘要翻译：提供了一种用于处理器中早期指令文本操作数存储比较避免的方法和系统。该系统包括用于处理指令流中的指令文本的处理器流水线，其中指令文本包括操作数地址信息。该系统还包括监视指令流的延迟逻辑。延迟逻辑执行一种方法，其包括检测在指令流中的存储指令之后的加载指令，将存储指令的操作数地址信息与加载指令进行比较。响应于检测存储指令的操作数地址信息和加载指令之间的公共字段值，该方法还包括延迟处理器流水线中的加载指令。

3. 发明申请

US20090210675A1 METHOD AND SYSTEM FOR EARLY INSTRUCTION TEXT BASED OPERAND STORE COMPARE REJECT AVOIDANCE 失效
标题翻译：用于早期指导文本操作的方法和系统存储比较对象避免
公开(公告)号：US20090210675A1
公开(公告)日：2009-08-20
申请号：US12034042
申请日：2008-02-20
申请人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung K. Shum
发明人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung K. Shum
IPC分类号： G06F9/30
CPC分类号： G06F9/3826 , G06F9/3016 , G06F9/382 , G06F9/3834 , G06F9/3836 , G06F9/3861
摘要： A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address information. The system also includes delay logic to monitor the instruction stream. The delay logic performs a method that includes detecting a load instruction following a store instruction in the instruction stream, comparing the operand address information of the store instruction with the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to detecting a common field value between the operand address information of the store instruction and the load instruction.
摘要翻译：提供了一种用于处理器中早期指令文本操作数存储比较避免的方法和系统。该系统包括用于处理指令流中的指令文本的处理器流水线，其中指令文本包括操作数地址信息。该系统还包括监视指令流的延迟逻辑。延迟逻辑执行一种方法，其包括检测在指令流中的存储指令之后的加载指令，将存储指令的操作数地址信息与加载指令进行比较。响应于检测存储指令的操作数地址信息和加载指令之间的公共字段值，该方法还包括延迟处理器流水线中的加载指令。

4. 发明授权

US08195924B2 Early instruction text based operand store compare reject avoidance 失效
标题翻译：早期指令文本操作数存储比较拒绝回避
公开(公告)号：US08195924B2
公开(公告)日：2012-06-05
申请号：US13050484
申请日：2011-03-17
申请人： Khary J. Alexander , Fadi Y. Basuba , Bruce C. Giamei , David S. Hutton , Chung-Lung K. Shum
发明人： Khary J. Alexander , Fadi Y. Basuba , Bruce C. Giamei , David S. Hutton , Chung-Lung K. Shum
IPC分类号： G06F9/312
CPC分类号： G06F9/3826 , G06F9/3016 , G06F9/382 , G06F9/3834 , G06F9/3836 , G06F9/3861
摘要： A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address information. The system also includes delay logic to monitor the instruction stream. The delay logic performs a method that includes detecting a load instruction following a store instruction in the instruction stream, comparing the operand address information of the store instruction with the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to detecting a common field value between the operand address information of the store instruction and the load instruction.
摘要翻译：提供了一种用于处理器中早期指令文本操作数存储比较避免的方法和系统。该系统包括用于处理指令流中的指令文本的处理器流水线，其中指令文本包括操作数地址信息。该系统还包括监视指令流的延迟逻辑。延迟逻辑执行一种方法，其包括检测在指令流中的存储指令之后的加载指令，将存储指令的操作数地址信息与加载指令进行比较。响应于检测存储指令的操作数地址信息和加载指令之间的公共字段值，该方法还包括延迟处理器流水线中的加载指令。

5. 发明申请

US20130339666A1 SPECIAL CASE REGISTER UPDATE WITHOUT EXECUTION 审中-公开
公开(公告)号：US20130339666A1
公开(公告)日：2013-12-19
申请号：US13524471
申请日：2012-06-15
申请人： Gregory W. Alexander , Brian D. Barrick , Fadi Y. Busaba , Bruce C. Giamei , Edward T. Malley , Chung-Lung K. Shum
发明人： Gregory W. Alexander , Brian D. Barrick , Fadi Y. Busaba , Bruce C. Giamei , Edward T. Malley , Chung-Lung K. Shum
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30043 , G06F9/3017 , G06F9/384
摘要： A method of changing a value of associated with a logical address in a computing device. The method includes: receiving an instruction at an instruction decoder, the instruction including a target register expressed as a logical value; determining at an instruction decoder that a result of the instruction is to set the target register to a constant value, the target register being in a physical register file associated with an execution unit; and mapping, in a register mapper, the logical address to a location represented by a special register tag.

6. 发明授权

US09280398B2 Major branch instructions 有权
公开(公告)号：US09280398B2
公开(公告)日：2016-03-08
申请号：US13362574
申请日：2012-01-31
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/30 , G06F9/40 , G06F9/46 , G06F9/52 , G06F9/38 , G06F9/32
CPC分类号： G06F9/528 , G06F9/3005 , G06F9/30145 , G06F9/322 , G06F9/3804 , G06F9/3842 , G06F9/3851 , G06F9/46 , G06F9/466 , G06F9/467
摘要： Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of processing at the other segment of code enabling execution of the other segment of code to be performed in parallel with the segment of code from which the branch was taken. In one example, the other stream of processing starts a transaction for processing instructions of the other stream of processing.

7. 发明授权

US08904246B2 Variable acknowledge rate to reduce bus contention in presence of communication errors 有权
标题翻译：在存在通信错误的情况下减少总线争用的可变确认速率
公开(公告)号：US08904246B2
公开(公告)日：2014-12-02
申请号：US13458522
申请日：2012-04-27
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F11/00
CPC分类号： H04L1/08 , H04L1/1864 , H04L2001/0094
摘要： A variable write back indicator control is provided to control the amount of data to be re-transmitted when a packet error occurs. A hardware controller obtains an indication that an acknowledge rate or an amount of set write back indicators of a data frame is to be adjusted. The indication is based on an error rate of data transmission over a communication bus. Based on obtaining the indication that the amount of set write back indicators is to be adjusted, one or more write back indicators are adjusted.
摘要翻译：提供可变写回指示器控件来控制发生数据包错误时要重新发送的数据量。硬件控制器获得要调整数据帧的确认速率或设置回写指示符量的指示。该指示基于通过通信总线的数据传输的错误率。基于获取设定回写指示器的数量的指示，调整一个或多个回写指示符。

8. 发明授权

US08904100B2 Process identifier-based cache data transfer 有权
标题翻译：基于进程标识符的缓存数据传输
公开(公告)号：US08904100B2
公开(公告)日：2014-12-02
申请号：US13493636
申请日：2012-06-11
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F12/02
CPC分类号： G06F17/30982 , G06F12/0817 , G06F12/12
摘要： Embodiments of the invention relate to process identifier (PID) based cache information transfer. An aspect of the invention includes sending, by a first core of a processor, a PID associated with a cache miss in a first local cache of the first core to a second cache of the processor. Another aspect of the invention includes determining that the PID associated with the cache miss is listed in a PID table of the second cache. Yet another aspect of the invention includes based on the PID being listed in the PID table of the second cache, determining a plurality of entries in a cache directory of the second cache that are associated with the PID. Yet another aspect of the invention includes pushing cache information associated with each of the determined plurality of entries in the cache directory from the second cache to the first local cache.
摘要翻译：本发明的实施例涉及基于过程标识符（PID）的高速缓存信息传送。本发明的一个方面包括由处理器的第一核心将与第一核心的第一本地高速缓存中的高速缓存未命中相关联的PID发送到处理器的第二高速缓存。本发明的另一方面包括确定与高速缓存未命中相关联的PID被列在第二高速缓存的PID表中。本发明的另一方面包括基于PID列在第二高速缓存的PID表中，确定与PID相关联的第二高速缓存的高速缓存目录中的多个条目。本发明的另一方面包括将高速缓存目录中的确定的多个条目中的每一个相关联的缓存信息从第二高速缓存推送到第一本地高速缓存。

9. 发明申请

US20130290802A1 VARIABLE ACKNOWLEDGE RATE TO REDUCE BUS CONTENTION IN PRESENCE OF COMMUNICATION ERRORS 有权
标题翻译：在通信错误存在的情况下，可降低总线容量的可变确认值
公开(公告)号：US20130290802A1
公开(公告)日：2013-10-31
申请号：US13458522
申请日：2012-04-27
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： H03M13/00 , G06F11/08
CPC分类号： H04L1/08 , H04L1/1864 , H04L2001/0094
摘要： A variable write back indicator control is provided to control the amount of data to be re-transmitted when a packet error occurs. A hardware controller obtains an indication that an acknowledge rate or an amount of set write back indicators of a data frame is to be adjusted. The indication is based on an error rate of data transmission over a communication bus. Based on obtaining the indication that the amount of set write back indicators is to be adjusted, one or more write back indicators are adjusted.
摘要翻译：提供可变写回指示器控件来控制发生数据包错误时要重新发送的数据量。硬件控制器获得要调整数据帧的确认速率或设置回写指示符量的指示。该指示基于通过通信总线的数据传输的错误率。基于获取设定回写指示器的数量的指示，调整一个或多个回写指示符。

10. 发明授权

US08930950B2 Management of migrating threads within a computing environment to transform multiple threading mode processors to single thread mode processors 有权
标题翻译：在计算环境中迁移线程的管理，以将多个线程模式处理器转换为单线程模式处理器
公开(公告)号：US08930950B2
公开(公告)日：2015-01-06
申请号：US13353550
申请日：2012-01-19
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50
CPC分类号： G06F9/4856 , G06F9/505 , G06F9/5088
摘要： Threads of a computing environment are managed to improve system performance. Threads are migrated between processors to take advantage of single thread processing mode, when possible. As an example, inactive threads are migrated from one or more processors, potentially freeing-up one or more processors to execute an active thread. Active threads are migrated from one processor to another to transform multiple threading mode processors to single thread mode processors.
摘要翻译：管理计算环境的线程以提高系统性能。线程在处理器之间迁移，以尽可能利用单线程处理模式。作为示例，非活动线程从一个或多个处理器迁移，潜在地释放一个或多个处理器以执行活动线程。活动线程从一个处理器迁移到另一个处理器，以将多个线程模式处理器转换为单线程模式处理器。

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