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1. 发明授权

US06057206A Mark protection scheme with no masking 有权
标题翻译：标记保护方案，无掩蔽
公开(公告)号：US06057206A
公开(公告)日：2000-05-02
申请号：US410526
申请日：1999-10-01
申请人： Khanh B. Nguyen , Marina Plat , Christopher F. Lyons , Harry J. Levinson
发明人： Khanh B. Nguyen , Marina Plat , Christopher F. Lyons , Harry J. Levinson
IPC分类号： H01L23/544 , H01L21/76
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/54493 , H01L2924/0002
摘要： A method of forming an alignment mark protection structure is disclosed and includes forming an alignment mark protection layer over a substrate which has an alignment mark associated therewith. The method also includes forming a negative photoresist layer over the alignment mark protection layer and removing a portion of the negative photoresist layer which does not overlie the alignment mark. The removal exposes a portion of the alignment mark protection layer which does not overlie the alignment mark and the exposed portion of the alignment mark protection layer is then removed. Preferably, the removal of a portion of the negative photoresist includes selectively exposing a peripheral portion thereof using an edge-bead removal tool, thereby allowing for the formation of an alignment mark protection structure without an extra masking step.
摘要翻译：公开了一种形成对准标记保护结构的方法，并且包括在具有与其相关联的对准标记的衬底上形成对准标记保护层。该方法还包括在对准标记保护层上形成负光致抗蚀剂层，并且去除不覆盖对准标记的负光致抗蚀剂层的一部分。去除暴露出不覆盖对准标记的对准标记保护层的一部分，然后去除对准标记保护层的暴露部分。优选地，去除负光致抗蚀剂的一部分包括使用边缘珠去除工具选择性地暴露其周边部分，从而允许形成对准标记保护结构而没有额外的掩模步骤。

2. 发明授权

US06255202B1 Damascene T-gate using a spacer flow 有权
标题翻译：大马士革T型门采用间隔流
公开(公告)号：US06255202B1
公开(公告)日：2001-07-03
申请号：US09619836
申请日：2000-07-20
申请人： Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh , Marina Plat
发明人： Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh , Marina Plat
IPC分类号： H01L213205
CPC分类号： H01L29/66583 , H01L21/28114 , H01L21/28123 , H01L21/76807 , H01L29/4238 , H01L29/4925
摘要： A method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer and an insulating layer over the gate oxide layer. An opening is formed extending partially into the insulating layer. The opening in the insulating layer extends from a top surface of the insulating layer to a first depth. Spacers are then formed on the sides of the opening. The opening is then extended in the insulating layer from the first depth to a second depth. The opening is wider from the top surface of the insulating layer to the first depth than the opening is from the first depth to the second depth. The spacers are then removed from the opening. The opening is then filled with a conductive material to form a T-gate structure.
摘要翻译：提供了一种制造T型栅结构的方法。提供一种结构，其具有硅层，该硅层具有栅极氧化物层，栅极氧化物层上的多晶硅层和栅极氧化物层上的绝缘层。形成部分地延伸到绝缘层中的开口。绝缘层中的开口从绝缘层的顶表面延伸到第一深度。然后在开口的两侧形成隔板。然后将开口在绝缘层中从第一深度延伸到第二深度。开口从绝缘层的顶表面到比第一深度从第一深度到第二深度的第一深度更宽。然后将隔离物从开口中取出。然后用导电材料填充开口以形成T形栅结构。

3. 发明授权

US06417084B1 T-gate formation using a modified conventional poly process 有权
标题翻译：使用改进的常规聚合方法形成T形栅
公开(公告)号：US06417084B1
公开(公告)日：2002-07-09
申请号：US09620300
申请日：2000-07-20
申请人： Bhanwar Singh , Marina Plat , Ramkumar Subramanian , Christopher F. Lyons
发明人： Bhanwar Singh , Marina Plat , Ramkumar Subramanian , Christopher F. Lyons
IPC分类号： H01L213205
CPC分类号： H01L21/28114 , H01L21/32139
摘要： A method is provided for fabricating a T-gate structure. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer, and an ARC layer over the polysilicon layer. A gate structure is formed by removing the ARC layer and a portion of the polysilicon layer around a gate region. Spacers are then formed around the gate structure. Undercut regions are formed in the gate structure by performing an isotropic etch to provide the gate structure with a base region and a contact region. The base region has a width smaller than the contact region.
摘要翻译：提供了一种用于制造T型栅结构的方法。提供一种结构，其具有硅层，该硅层具有栅极氧化物层，栅极氧化物层上的多晶硅层以及多晶硅层上的ARC层。通过在栅极区域周围除去ARC层和多晶硅层的一部分来形成栅极结构。然后在栅极结构周围形成间隔物。通过执行各向同性蚀刻在栅极结构中形成底切区域，以向栅极结构提供基极区域和接触区域。基部区域的宽度小于接触区域。

4. 发明授权

US06319802B1 T-gate formation using modified damascene processing with two masks 有权
标题翻译：使用具有两个掩模的改良镶嵌加工的T形栅结构
公开(公告)号：US06319802B1
公开(公告)日：2001-11-20
申请号：US09620145
申请日：2000-07-20
申请人： Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh , Marina Plat
发明人： Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh , Marina Plat
IPC分类号： H01L213205
CPC分类号： H01L21/28114
摘要： A method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer and a sacrificial layer over the protection layer. An opening is then formed in the sacrificial layer. A contact material is deposited over the sacrificial layer filling the opening with the contact material and forming a contact layer. Portions of the contact material outside a gate region are then removed. Finally, the sacrificial layer and portions of the protection layer and the gate oxide layer not forming a part of the T-gate structure are removed.
摘要翻译：提供了一种制造T型栅结构的方法。提供了一种具有硅层的结构，该硅层具有栅极氧化物层，栅极氧化物层上的保护层和保护层上的牺牲层。然后在牺牲层中形成开口。接触材料沉积在用接触材料填充开口的牺牲层上并形成接触层。然后去除栅极区域外部的接触材料的部分。最后，除去牺牲层和不形成T栅结构的一部分的保护层和栅极氧化物层的部分。

5. 发明授权

US06403456B1 T or T/Y gate formation using trim etch processing 有权
标题翻译： T或T / Y栅极形成
公开(公告)号：US06403456B1
公开(公告)日：2002-06-11
申请号：US09643611
申请日：2000-08-22
申请人： Marina Plat , Christopher F. Lyons , Bhanwar Singh , Ramkumar Subramanian
发明人： Marina Plat , Christopher F. Lyons , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： H01L2128
CPC分类号： H01L29/42376 , H01L21/28114 , H01L21/28123 , H01L21/76802
摘要： A method for fabricating a T-gate structure is provided. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second sacrificial layer over the first sacrificial layer. A photoresist layer is formed over the second sacrificial layer. An opening is formed in the photoresist layer. An opening is then formed in the second sacrificial layer beneath the opening in the photoresist layer. The opening is then expanded in the photoresist layer to expose portions of the top surface of the second sacrificial layer around the opening in the second sacrificial layer. The opening is extended in the second sacrificial layer through the first sacrificial layer and the opening is expanded in the second sacrificial layer to form a T-shaped opening in the first and second sacrificial layers. The photoresist layer is removed and the T-shaped opening is filled with a conductive material.
摘要翻译：提供了一种制造T型栅结构的方法。该方法包括以下步骤：提供具有栅极氧化物层的硅层，栅极氧化物层上的保护层，保护层上的第一牺牲层和第一牺牲层上的第二牺牲层。在第二牺牲层上形成光致抗蚀剂层。在光致抗蚀剂层中形成开口。然后在光致抗蚀剂层中的开口下方的第二牺牲层中形成开口。然后在光致抗蚀剂层中扩展开口，以暴露第二牺牲层的顶表面的部分围绕第二牺牲层中的开口。所述开口在所述第二牺牲层中延伸穿过所述第一牺牲层，并且所述开口在所述第二牺牲层中膨胀以在所述第一和第二牺牲层中形成T形开口。去除光致抗蚀剂层，并用导电材料填充T形开口。

6. 发明授权

US06313019B1 Y-gate formation using damascene processing 有权
标题翻译：使用大马士革加工的Y型门形成
公开(公告)号：US06313019B1
公开(公告)日：2001-11-06
申请号：US09643343
申请日：2000-08-22
申请人： Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh , Marina Plat
发明人： Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh , Marina Plat
IPC分类号： H01L2144
CPC分类号： H01L21/28114 , H01L29/42376 , Y10S438/978
摘要： A method for fabricating a Y-gate structure is provided. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second sacrificial layer over the first sacrificial layer. An inwardly sloping opening is formed in the second sacrificial layer and the opening is extended vertically in the first sacrificial layer. A contact material is deposited over the second sacrificial layer filling the opening with the contact material and forming a contact layer and portions of the contact material outside a gate region are removed. The first sacrificial layer and the second sacrificial layer are then removed.
摘要翻译：提供一种制造Y栅极结构的方法。该方法包括以下步骤：提供具有栅极氧化物层的硅层，栅极氧化物层上的保护层，保护层上的第一牺牲层和第一牺牲层上的第二牺牲层。在第二牺牲层中形成向内倾斜的开口，并且开口在第一牺牲层中垂直延伸。接触材料沉积在用接触材料填充开口的第二牺牲层上，并形成接触层，并且去除栅极区域外部的接触材料的部分。然后去除第一牺牲层和第二牺牲层。

7. 发明授权

US06270929B1 Damascene T-gate using a relacs flow 有权
标题翻译：大马士革T门使用相关资料流
公开(公告)号：US06270929B1
公开(公告)日：2001-08-07
申请号：US09619789
申请日：2000-07-20
申请人： Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh , Marina Plat
发明人： Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh , Marina Plat
IPC分类号： H01L21302
CPC分类号： H01L21/28114 , H01L21/0273 , H01L21/0338 , H01L21/31144 , H01L21/76802 , H01L29/42376
摘要： A method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer and an insulating layer over the gate oxide layer. A photoresist layer is formed over the insulating layer. An opening is the formed extending through the photoresist layer and partially into the insulating layer. The opening in the insulating layer extends from a top surface of the insulating layer to a first depth. The photoresist layer is swelled to reduce the size of the opening in the photoresist layer. The opening is then extended in the insulating layer from the first depth to a second depth. The opening is wider from the top surface of the insulating layer to the first depth than the opening is from the first depth to the second depth. The opening is then filled with a conductive material to form a T-gate structure.
摘要翻译：提供了一种制造T型栅结构的方法。提供一种结构，其具有硅层，该硅层具有栅极氧化物层，栅极氧化物层上的多晶硅层和栅极氧化物层上的绝缘层。在绝缘层上形成光致抗蚀剂层。开口形成为延伸穿过光致抗蚀剂层并部分地进入绝缘层。绝缘层中的开口从绝缘层的顶表面延伸到第一深度。光致抗蚀剂层被膨胀以减小光致抗蚀剂层中的开口的尺寸。然后将开口在绝缘层中从第一深度延伸到第二深度。开口从绝缘层的顶表面到比第一深度从第一深度到第二深度的第一深度更宽。然后用导电材料填充开口以形成T形栅结构。

8. 发明授权

US06306769B1 Use of dual patterning masks for printing holes of small dimensions 有权
标题翻译：使用双图案掩模打印小尺寸的孔
公开(公告)号：US06306769B1
公开(公告)日：2001-10-23
申请号：US09494698
申请日：2000-01-31
申请人： Ramkumar Subramanian , Marina Plat
发明人： Ramkumar Subramanian , Marina Plat
IPC分类号： H01L21311
CPC分类号： G03F7/70466 , G03F7/0035 , G03F7/203 , H01L21/31144 , H01L21/76807
摘要： The present invention addresses a problem associated with exposing a photoresist layer of non-uniform thickness. Oftentimes, trench patterns etched into a layer of a semiconductor structure will have trenches of varying sizes. Larger trenches in the structure become filled with photoresist material, while smaller trenches do not leading to non-uniformity of photoresist layer thickness with respect to the large and small trenches. The present invention addresses this non-uniformity in photoresist layer thickness by employing at least two exposure steps when exposing the photoresist layer. A first exposure step exposes portions of the photoresist layer corresponding to the large trenches using a first reticle and first energy level. Next, a second exposure step exposes portions of the photoresist layer corresponding to the small trenches using a second reticle and second energy level. The first and second energy levels corresponding to proper exposure of the respective photoresist layer portions of different thicknesses.
摘要翻译：本发明解决了暴露不均匀厚度的光致抗蚀剂层的问题。通常，蚀刻到半导体结构层中的沟槽图案将具有不同尺寸的沟槽。结构中较大的沟槽被光致抗蚀剂材料填充，而较小的沟槽不会相对于大的和小的沟槽导致光致抗蚀剂层厚度的不均匀性。本发明通过在曝光光致抗蚀剂层时采用至少两个曝光步骤来解决光致抗蚀剂层厚度的这种不均匀性。第一曝光步骤使用第一掩模版和第一能级暴露对应于大沟槽的光致抗蚀剂层的部分。接下来，第二曝光步骤使用第二掩模版和第二能级暴露对应于小沟槽的光致抗蚀剂层的部分。第一和第二能量水平对应于不同厚度的各个光致抗蚀剂层部分的适当曝光。

9. 发明申请

US20050020019A1 Method for semiconductor gate line dimension reduction 有权
标题翻译：半导体栅极线尺寸减小的方法
公开(公告)号：US20050020019A1
公开(公告)日：2005-01-27
申请号：US10922093
申请日：2004-08-19
申请人： Douglas Bonser , Marina Plat , Chih Yang , Scott Bell , Srikanteswara Dakshina-Murthy , Philip Fisher , Christopher Lyons
发明人： Douglas Bonser , Marina Plat , Chih Yang , Scott Bell , Srikanteswara Dakshina-Murthy , Philip Fisher , Christopher Lyons
IPC分类号： H01L21/28 , H01L21/336 , H01L29/10 , H01L21/3205
CPC分类号： H01L29/66477 , H01L21/28123 , H01L29/1045 , H01L29/1054 , H01L29/665
摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.
摘要翻译：为了减小MOSFET栅极的宽度，栅极形成有在其上形成的硬掩模。然后执行各向同性蚀刻以修剪栅极，以便减小栅极的宽度。所得到的栅极可以形成为比仅通过常规投影光刻技术可实现的最小宽度窄的宽度。

10. 发明授权

US06606738B1 Analytical model for predicting the operating process window for lithographic patterning techniques based on photoresist trim technology 失效
标题翻译：基于光刻胶修剪技术的光刻图案化技术预测工作过程窗口分析模型
公开(公告)号：US06606738B1
公开(公告)日：2003-08-12
申请号：US09822993
申请日：2001-03-30
申请人： Scott Bell , Marina Plat , Amada Wilkison , Chih-Yuh Yang
发明人： Scott Bell , Marina Plat , Amada Wilkison , Chih-Yuh Yang
IPC分类号： G06F1750
CPC分类号： G03F7/40 , H01L21/31138 , H01L21/32139
摘要： In the present method of trimming photoresist to form a mask for a layer of a semiconductor device, which layer may include polysilicon and/or nitride, the method is practiced substantially in accordance with: wmin=(h0−Rvtmax)/ARmax where w1=minimum width of trimmed photoresist; h0=height of photoresist prior to trim; Rv=resist vertical etch rate; tmax=maximum etch time to reach resist vertical etch limit; ARmax=maximum allowable aspect ratio of trimmed photoresist. The present invention is further a method of trimming photoresist to form a mask for a layer of a semiconductor device, which layer may include polysilicon and/or nitride, and which method is practiced substantially in accordance with: w0=(h0−Rvtmax)/ARmax+Rhtmax where w0=width of photoresist prior to trim; h0=height of photoresist prior to trim; Rv=resist vertical etch rate; tmax=maximum etch time to reach resist vertical etch limit; ARmax=maximum allowable aspect ratio of trimmed photoresist; Rh=horizontal resist etch rate.
摘要翻译：在本发明的光刻胶修整方法中，为了形成半导体器件层的掩模，该层可以包括多晶硅和/或氮化物，该方法基本上按以下方式实施：其中w1 =修整的光致抗蚀剂的最小宽度; h0 = 光刻胶在修剪之前; Rv =抗蚀剂垂直蚀刻速率; tmax =达到抗蚀剂垂直蚀刻极限的最大蚀刻时间; ARmax =修剪光致抗蚀剂的最大允许纵横比。本发明还涉及一种修整光致抗蚀剂以形成半导体器件层的掩模的方法，该层可包括多晶硅和/或氮化物，并且该方法基本上按照其中：w0 =修剪之前的光致抗蚀剂的宽度; h0 =修剪前光致抗蚀剂的高度; Rv =抗蚀剂垂直蚀刻速率; tmax =达到抗蚀剂垂直蚀刻极限的最大蚀刻时间; ARmax =修剪光致抗蚀剂的最大允许纵横比; Rh =水平抗蚀剂蚀刻速率。

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