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    • 1. 发明授权
    • Mark protection scheme with no masking
    • 标记保护方案,无掩蔽
    • US06057206A
    • 2000-05-02
    • US410526
    • 1999-10-01
    • Khanh B. NguyenMarina PlatChristopher F. LyonsHarry J. Levinson
    • Khanh B. NguyenMarina PlatChristopher F. LyonsHarry J. Levinson
    • H01L23/544H01L21/76
    • H01L23/544H01L2223/54426H01L2223/54453H01L2223/54493H01L2924/0002
    • A method of forming an alignment mark protection structure is disclosed and includes forming an alignment mark protection layer over a substrate which has an alignment mark associated therewith. The method also includes forming a negative photoresist layer over the alignment mark protection layer and removing a portion of the negative photoresist layer which does not overlie the alignment mark. The removal exposes a portion of the alignment mark protection layer which does not overlie the alignment mark and the exposed portion of the alignment mark protection layer is then removed. Preferably, the removal of a portion of the negative photoresist includes selectively exposing a peripheral portion thereof using an edge-bead removal tool, thereby allowing for the formation of an alignment mark protection structure without an extra masking step.
    • 公开了一种形成对准标记保护结构的方法,并且包括在具有与其相关联的对准标记的衬底上形成对准标记保护层。 该方法还包括在对准标记保护层上形成负光致抗蚀剂层,并且去除不覆盖对准标记的负光致抗蚀剂层的一部分。 去除暴露出不覆盖对准标记的对准标记保护层的一部分,然后去除对准标记保护层的暴露部分。 优选地,去除负光致抗蚀剂的一部分包括使用边缘珠去除工具选择性地暴露其周边部分,从而允许形成对准标记保护结构而没有额外的掩模步骤。
    • 5. 发明授权
    • Ultra-thin resist shallow trench process using high selectivity nitride etch
    • 使用高选择性氮化物蚀刻的超薄抗蚀剂浅沟槽工艺
    • US06740566B2
    • 2004-05-25
    • US09398641
    • 1999-09-17
    • Christopher F. LyonsScott A. BellHarry J. LevinsonKhanh B. NguyenFei WangChih Yuh Yang
    • Christopher F. LyonsScott A. BellHarry J. LevinsonKhanh B. NguyenFei WangChih Yuh Yang
    • H01L2176
    • H01L21/76224
    • In one embodiment, the present invention relates to a method of forming a shallow trench, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a nitride layer over the barrier oxide layer; depositing an ultra-thin photoresist over the nitride layer, the ultra-thin photoresist having a thickness of about 2,000 Å or less; patterning the ultra-thin photoresist to expose a portion of the nitride layer and to define a pattern for the shallow trench; etching the exposed portion of the nitride layer with an etchant having a nitride:photoresist selectivity of at least about 10:1 to expose a portion of the barrier oxide layer; etching the exposed portion of the barrier oxide layer to expose a portion of the semiconductor substrate; and etching the exposed portion of the semiconductor substrate to provide the shallow trench. In another embodiment, the method further involves depositing an insulating filler material into the shallow trench to provide a shallow trench isolation region.
    • 在一个实施例中,本发明涉及一种形成浅沟槽的方法,包括以下步骤:在半导体衬底上提供包括阻挡氧化物层的半导体衬底,以及在阻挡氧化物层上方的氮化物层; 在所述氮化物层上沉积超薄光致抗蚀剂,所述超薄光致抗蚀剂具有约2,000或更小的厚度; 图案化超薄光致抗蚀剂以暴露氮化物层的一部分并且限定用于浅沟槽的图案; 用具有至少约10:1的氮化物:光致抗蚀剂选择性的蚀刻剂蚀刻氮化物层的暴露部分以暴露部分阻挡氧化物层; 蚀刻阻挡氧化物层的暴露部分以暴露半导体衬底的一部分; 并蚀刻半导体衬底的暴露部分以提供浅沟槽。 在另一个实施例中,该方法还包括将绝缘填充材料沉积到浅沟槽中以提供浅沟槽隔离区域。