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1. 发明授权

US5477165A Programmable logic module and architecture for field programmable gate array device 失效
标题翻译：现场可编程门阵列器件的可编程逻辑模块和架构
公开(公告)号：US5477165A
公开(公告)日：1995-12-19
申请号：US332550
申请日：1994-12-28
申请人： Khaled A. ElAyat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
发明人： Khaled A. ElAyat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
IPC分类号： H03K19/177 , G01R31/28 , G01R31/3185 , H03K19/173
CPC分类号： G01R31/2884 , G01R31/318519 , H03K19/17704 , H03K19/17728
摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.
摘要翻译：用户可编程门阵列架构包括可包括一个或多个组合和/或顺序逻辑电路的逻辑功能模块阵列。包括多个水平和垂直通用互连通道的互连架构，每个通道互连通道包括多个互连导体，其中一些互连导体可能被分段，其被施加在阵列上。互连导体中的单个导体可通过用户可编程互连元件彼此连接并连接到逻辑功能模块的输入和输出端。包括本地互连通道的本地互连架构也被施加在阵列上。每个局部互连通道包括多个局部互连导体并且在相邻的逻辑功能模块对之间运行。

2. 发明授权

US5698992A Programmable logic module and architecture for field programmable gate array device 失效
标题翻译：现场可编程门阵列器件的可编程逻辑模块和架构
公开(公告)号：US5698992A
公开(公告)日：1997-12-16
申请号：US746554
申请日：1996-11-13
申请人： Khaled A. El Ayat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
发明人： Khaled A. El Ayat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
IPC分类号： H03K19/177 , G01R31/28 , G01R31/3185 , H03K19/173
CPC分类号： G01R31/2884 , G01R31/318519 , H03K19/17704 , H03K19/17728
摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.
摘要翻译：用户可编程门阵列架构包括可包括一个或多个组合和/或顺序逻辑电路的逻辑功能模块阵列。包括多个水平和垂直通用互连通道的互连架构，每个通道互连通道包括多个互连导体，其中一些互连导体可能被分段，其被施加在阵列上。互连导体中的单个导体可通过用户可编程互连元件彼此连接并连接到逻辑功能模块的输入和输出端。包括本地互连通道的本地互连架构也被施加在阵列上。每个局部互连通道包括多个局部互连导体并且在相邻的逻辑功能模块对之间运行。

3. 发明授权

US5606267A Programmable logic module and architecture for field programmable gate array device 失效
公开(公告)号：US5606267A
公开(公告)日：1997-02-25
申请号：US522945
申请日：1995-09-01
申请人： Khaled A. El Ayat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
发明人： Khaled A. El Ayat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
IPC分类号： H03K19/177 , G01R31/28 , G01R31/3185 , H03K19/173
CPC分类号： G01R31/2884 , G01R31/318519 , H03K19/17704 , H03K19/17728
摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

4. 发明授权

US5952847A Multiple logic family compatible output driver 失效
标题翻译：多逻辑系列兼容输出驱动器
公开(公告)号：US5952847A
公开(公告)日：1999-09-14
申请号：US673701
申请日：1996-06-25
申请人： William C. Plants , Gregory W. Bakker
发明人： William C. Plants , Gregory W. Bakker
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/088 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018521
摘要： The output buffer circuit according to the present invention is connected to an I/O pad of the integrated circuit. The output buffer circuit includes an output totem pole, a level shifter and enable logic. The output totem pole has a first input connected to the level shifter and a second input connected to the enable logic. The output of the totem pole is connected to an I/O pad. The totem pole includes a pullup transistor connected to 3.3 volt Vcc and a pulldown transistor connected to ground. In a first embodiment of the invention, the pullup transistor in the totem pole is an N-channel MOS transistor, and in a second embodiment of the invention, the pullup transistor in the totem pole is a P-channel MOS transistor formed in an N-well tied to the 5 volt Vcc. In the first embodiment of the present invention, the N-Channel MOS pullup transistor is turned on by a 5 volt signal from the level shifter. In the second embodiment of the present invention, the P-Channel MOS pullup transistor is turned on by a ground level signal from the level shifter. The enable logic drives the output of the totem pole in response to input signals to the enable logic. The inputs to the enable logic are a Data input, a Global enable input and an Output enable input.
摘要翻译：根据本发明的输出缓冲器电路连接到集成电路的I / O焊盘。输出缓冲电路包括输出图腾柱，电平移位器和使能逻辑。输出图腾柱具有连接到电平移位器的第一输入端和连接到使能逻辑的第二输入端。图腾柱的输出连接到I / O焊盘。图腾柱包括连接到3.3伏Vcc的上拉晶体管和连接到地的下拉晶体管。在本发明的第一实施例中，图腾柱中的上拉晶体管是N沟道MOS晶体管，在本发明的第二实施例中，图腾柱中的上拉晶体管是形成在N沟道MOS晶体管中的P沟道MOS晶体管 - 连接到5伏Vcc。在本发明的第一实施例中，N沟道MOS上拉晶体管由来自电平移位器的5伏特信号导通。在本发明的第二实施例中，P沟道MOS上拉晶体管由来自电平移位器的接地电平信号导通。响应于使能逻辑的输入信号，使能逻辑驱动图腾柱的输出。使能逻辑的输入是数据输入，全局使能输入和输出使能输入。

5. 发明授权

US08067959B2 Programmable delay line compensated for process, voltage, and temperature 有权
标题翻译：可编程延迟线补偿过程，电压和温度
公开(公告)号：US08067959B2
公开(公告)日：2011-11-29
申请号：US12716469
申请日：2010-03-03
申请人： William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek P. Jasinoski
发明人： William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek P. Jasinoski
IPC分类号： H03K19/173 , H03K25/00
CPC分类号： H03K5/131 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143 , H03K2005/00156 , H03L7/07 , H03L7/0805 , H03L7/0814 , H03L7/10
摘要： A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.
摘要翻译：补偿过程，电压和温度变化的延迟线包括被配置为将数字信号延迟数字信号的时钟周期的延迟锁定环（DLL），该DLL包括布置为多个级联子串的DLL延迟线为了响应于数字控制信号，延迟每个子延迟线提供多个延迟量子中的一个。分馏电路被配置为产生作为数字控制信号的一部分的数字延迟线控制信号。数字延迟线被布置为多个级联子延迟线，每个子延迟线响应于数字延迟线控制信号提供多个延迟量子中的一个。

6. 发明申请

US20100156459A1 PROGRAMMABLE DELAY LINE COMPENSATED FOR PROCESS, VOLTAGE, AND TEMPERATURE 有权
标题翻译：可编程延迟线补偿过程，电压和温度
公开(公告)号：US20100156459A1
公开(公告)日：2010-06-24
申请号：US12716469
申请日：2010-03-03
申请人： William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek P. Jasionowski
发明人： William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek P. Jasionowski
IPC分类号： H03K19/177 , H03L7/06
CPC分类号： H03K5/131 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143 , H03K2005/00156 , H03L7/07 , H03L7/0805 , H03L7/0814 , H03L7/10
摘要： A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.
摘要翻译：补偿过程，电压和温度变化的延迟线包括被配置为将数字信号延迟数字信号的时钟周期的延迟锁定环（DLL），该DLL包括布置为多个级联子串的DLL延迟线为了响应于数字控制信号，延迟每个子延迟线提供多个延迟量子中的一个。分馏电路被配置为产生作为数字控制信号的一部分的数字延迟线控制信号。数字延迟线被布置为多个级联子延迟线，每个子延迟线响应于数字延迟线控制信号提供多个延迟量子中的一个。

7. 发明授权

US07701246B1 Programmable delay line compensated for process, voltage, and temperature 失效
标题翻译：可编程延迟线补偿过程，电压和温度
公开(公告)号：US07701246B1
公开(公告)日：2010-04-20
申请号：US12175399
申请日：2008-07-17
申请人： William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek Jasionowski
发明人： William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek Jasionowski
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K5/131 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143 , H03K2005/00156 , H03L7/07 , H03L7/0805 , H03L7/0814 , H03L7/10
摘要： A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.
摘要翻译：补偿过程，电压和温度变化的延迟线包括被配置为将数字信号延迟数字信号的时钟周期的延迟锁定环（DLL），该DLL包括布置为多个级联子串的DLL延迟线为了响应于数字控制信号，延迟每个子延迟线提供多个延迟量子中的一个。分馏电路被配置为产生作为数字控制信号的一部分的数字延迟线控制信号。数字延迟线被布置为多个级联子延迟线，每个子延迟线响应于数字延迟线控制信号提供多个延迟量子中的一个。

8. 发明授权

US5508220A Method of forming antifuses having minimum areas 失效
标题翻译：形成具有最小面积的反熔丝的方法
公开(公告)号：US5508220A
公开(公告)日：1996-04-16
申请号：US243001
申请日：1993-06-01
申请人： Abdelshafy A. Eltoukhy , Gregory W. Bakker
发明人： Abdelshafy A. Eltoukhy , Gregory W. Bakker
IPC分类号： G11C17/06 , H01L21/82 , H01L23/525 , H01L21/70 , H01L27/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , Y10S148/055
摘要： Antifuses having minimum areas are formed by a process including the steps of forming doped regions in a semiconductor substrate, forming a dielectric layer over the surface of the substrate, performing masking and etching steps to form apertures in the dielectric layer over portions of the doped regions where antifuses are to be formed, depositing a second dielectric layer over the first dielectric layer and the apertures, the second dielectric layer having a faster etch rate than the first dielectric layer, etching the second dielectric layer to leave spacers at the edges of the apertures, forming the antifuse dielectric in the apertures, and forming upper antifuse electrodes over the antifuse dielectric. In another process, a process for forming antifuses includes the steps of forming a dielectric layer over the surface of a semiconductor substrate, forming a first layer of polysilicon over the insulating layer, forming apertures in between portions of the first polysilicon layer where antifuses are to be formed, doping the exposed regions in the substrate using the polysilicon as a masking member, depositing an oxide over the polysilicon regions, etching the oxide to expose the substrate between the regions of first layer polysilicon, forming the antifuse dielectric in the apertures, and forming upper antifuse electrodes over the antifuse dielectric. The process of the present invention may also be used to form antifuses in layers above the substrate.
摘要翻译：具有最小面积的防潮剂通过包括以下步骤的方法形成，该方法包括在半导体衬底中形成掺杂区域，在衬底的表面上形成介电层，进行掩模和蚀刻步骤以在掺杂区域的部分上形成介电层中的孔在要形成反熔丝的情况下，在所述第一介电层和所述孔之上沉积第二电介质层，所述第二电介质层具有比所述第一电介质层更快的蚀刻速率，蚀刻所述第二电介质层以在所述孔的边缘留下间隔物在孔中形成反熔丝电介质，并在反熔丝电介质上形成上部反熔丝电极。在另一种方法中，形成反熔丝的方法包括以下步骤：在半导体衬底的表面上形成电介质层，在绝缘层上形成第一多晶硅层，在反熔丝的第一多晶硅层的部分之间形成孔用多晶硅作为掩模构件掺杂衬底中的暴露区域，在多晶硅区域上沉积氧化物，蚀刻氧化物以在第一层多晶硅的区域之间露出衬底，在孔中形成反熔丝电介质，以及在反熔丝电介质上形成上部反熔丝电极。本发明的方法也可用于在基底上方形成层间的反熔丝。

9. 发明授权

US07932744B1 Staggered I/O groups for integrated circuits 有权
标题翻译：用于集成电路的交错I / O组
公开(公告)号：US07932744B1
公开(公告)日：2011-04-26
申请号：US12142118
申请日：2008-06-19
申请人： Jonathan W. Greene , Gregory W. Bakker , Suhail Zain
发明人： Jonathan W. Greene , Gregory W. Bakker , Suhail Zain
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： An I/O scheme for an integrated circuit includes a group layout cell. The group layout cell includes a plurality of signal I/O pads. A driver circuit is coupled to each signal I/O pad. The group layout cell also includes two I/O driver-circuit power-supply pads. ESD protection circuitry is coupled to the plurality of driver circuits. The signal I/O pads and the I/O driver-circuit power-supply pads are arranged in rows. The rows may be regular or staggered.
摘要翻译：集成电路的I / O方案包括组布局单元。组布局单元包括多个信号I / O焊盘。驱动器电路耦合到每个信号I / O焊盘。组布局单元还包括两个I / O驱动器电路电源板。 ESD保护电路耦合到多个驱动器电路。信号I / O焊盘和I / O驱动器电路电源板排列成行。行可以是规则的或交错的。

10. 发明授权

US5087958A Misalignment tolerant antifuse 失效
标题翻译：不对抗容错的反熔丝
公开(公告)号：US5087958A
公开(公告)日：1992-02-11
申请号：US609177
申请日：1990-11-05
申请人： Shih-Oh Chen , Steve S. Chiang , Gregory W. Bakker
发明人： Shih-Oh Chen , Steve S. Chiang , Gregory W. Bakker
IPC分类号： H01L21/82 , H01L23/525
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： A misalignment tolerant antifuse includes a lower electrode, bounded by a relatively thick first insulating layer, an upper electrode separated from the lower electrode by a second insulating layer having a thickness less than that of the first insulating layer, a pair of antifuse window regions in the second insulating layer, abutting the first insulating layer on opposite sides of the lower electrode, the insulating material in the window regions being thinner than the remainder of the second insulating layer, and an upper electrode disposed above the second insulating layer and lying over the pair of regions and at least a portion of the first insulating layer.

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