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1. 发明授权

US07075122B1 Thyristor device with carbon lifetime adjustment implant and its method of fabrication 失效
公开(公告)号：US07075122B1
公开(公告)日：2006-07-11
申请号：US10670881
申请日：2003-09-25
申请人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
发明人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
IPC分类号： H01L29/72
CPC分类号： H01L27/0817 , H01L29/7436 , H01L29/7455
摘要： In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.

2. 发明授权

US07858449B2 Thyristor device with carbon lifetime adjustment implant and its method of fabrication 失效
标题翻译：具有碳寿命调整植入物的晶闸管器件及其制造方法
公开(公告)号：US07858449B2
公开(公告)日：2010-12-28
申请号：US12367891
申请日：2009-02-09
申请人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
发明人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
IPC分类号： H01L29/72
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
摘要翻译：在制造半导体存储器件的方法中，晶闸管可以形成在半导体材料层中。可以在用于晶闸管的基极 - 发射极结区域中注入和退火碳以影响泄漏特性。因此可以选择碳的密度和/或轰击能量和/或退火，以建立连接的低电压，泄漏特性，基本上大于其没有碳的泄漏。在一个实施例中，注入碳的退火可以与半导体器件的其它注入区域的激活共同进行。

3. 发明授权

US07488626B1 Thyristor device with carbon lifetime adjustment implant and its method of fabrication 失效
标题翻译：具有碳寿命调整植入物的晶闸管器件及其制造方法
公开(公告)号：US07488626B1
公开(公告)日：2009-02-10
申请号：US11483859
申请日：2006-07-10
申请人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
发明人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
IPC分类号： H01L29/72
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
摘要翻译：在制造半导体存储器件的方法中，晶闸管可以形成在半导体材料层中。可以在用于晶闸管的基极 - 发射极结区域中注入和退火碳以影响泄漏特性。因此可以选择碳的密度和/或轰击能量和/或退火，以建立连接的低电压，泄漏特性，基本上大于其没有碳的泄漏。在一个实施例中，注入碳的退火可以与半导体器件的其它注入区域的激活共同进行。

4. 发明申请

US20090162979A1 THYRISTOR DEVICE WITH CARBON LIFETIME ADJUSTMENT IMPLANT AND ITS METHOD OF FABRICATION 失效
标题翻译：具有碳生物调节植入物的制造装置及其制造方法
公开(公告)号：US20090162979A1
公开(公告)日：2009-06-25
申请号：US12367891
申请日：2009-02-09
申请人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
发明人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
IPC分类号： H01L21/266
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
摘要翻译：在制造半导体存储器件的方法中，晶闸管可以形成在半导体材料层中。可以在用于晶闸管的基极 - 发射极结区域中注入和退火碳以影响泄漏特性。因此可以选择碳的密度和/或轰击能量和/或退火，以建立连接的低电压，泄漏特性，基本上大于其没有碳的泄漏。在一个实施例中，注入碳的退火可以与半导体器件的其它注入区域的激活共同进行。

5. 发明授权

US07491586B2 Semiconductor device with leakage implant and method of fabrication 失效
标题翻译：具有漏电注入的半导体器件及其制造方法
公开(公告)号：US07491586B2
公开(公告)日：2009-02-17
申请号：US11159514
申请日：2005-06-22
申请人： Andrew E Horch , Hyun-Jin Cho , Farid Nemati , Scott Robins , Rajesh N. Gupta , Kevin J. Yang
发明人： Andrew E Horch , Hyun-Jin Cho , Farid Nemati , Scott Robins , Rajesh N. Gupta , Kevin J. Yang
IPC分类号： H01L21/332 , H01L21/04 , H01L21/425
CPC分类号： G11C11/39 , H01L27/0817 , H01L29/7436 , H01L29/7455 , H01L29/749
摘要： A method of fabricating a thyristor-based memory may include forming different opposite conductivity-type regions in silicon for defining a thyristor and an access device in series relationship. An activation anneal may activate dopants previously implanted for the different regions. A damaging implant of germanium or xenon or argon may be directed into select regions of the silicon including at least one p-n junction region for the access device and the thyristor. A re-crystallization anneal may then be performed to re-crystallize at least some of the damaged lattice structure resulting from the damaging implant. The re-crystallization anneal may use a temperature less than that of the previous activation anneal.
摘要翻译：制造基于晶闸管的存储器的方法可以包括在硅中形成用于限定可控硅和串联连接的存取装置的不同的相反导电型区域。激活退火可以激活先前为不同区域植入的掺杂剂。可以将锗或氙或氩的有害植入物引导到硅的选择区域中，包括用于进入装置和晶闸管的至少一个p-n结区域。然后可以进行重结晶退火，以重新结晶由损伤性植入物引起的至少一些损伤的晶格结构。再结晶退火可以使用比先前激活退火的温度低的温度。

6. 发明授权

US07195959B1 Thyristor-based semiconductor device and method of fabrication 失效
标题翻译：基于晶闸管的半导体器件及其制造方法
公开(公告)号：US07195959B1
公开(公告)日：2007-03-27
申请号：US10958820
申请日：2004-10-04
申请人： James D. Plummer , Zachary K. Lee , Kevin J. Yang , Farid Nemati
发明人： James D. Plummer , Zachary K. Lee , Kevin J. Yang , Farid Nemati
IPC分类号： H01L21/332
CPC分类号： H01L29/74 , H01L21/84 , H01L27/1027 , H01L27/1203 , H01L29/66393 , H01L29/7436
摘要： A thyristor-based semiconductor memory device may comprise at least a region thereof, e.g., a p-base region, having high ionization energy impurity, such as a dopant. This high ionization energy impurity within a base region may be operable to compensate for a gain-versus-temperature dependence of a constituent bipolar transistor of the thyristor element of a thyristor-based memory device. In particular embodiments, the high ionization energy impurity may include a donor and/or acceptor in silicon.
摘要翻译：基于晶闸管的半导体存储器件可以至少包括具有高电离能杂质的诸如掺杂剂的区域，例如p基区域。基极区域内的这种高电离能杂质可以用于补偿基于晶闸管的存储器件的晶闸管元件的构成双极晶体管的增益 - 温度依赖性。在具体实施方案中，高电离能杂质可包括硅中的给体和/或受体。

7. 发明授权

US08093107B1 Thyristor semiconductor memory and method of manufacture 失效
标题翻译：晶闸管半导体存储器及其制造方法
公开(公告)号：US08093107B1
公开(公告)日：2012-01-10
申请号：US12271758
申请日：2008-11-14
申请人： Farid Nemati , Scott Robins , Kevin J. Yang
发明人： Farid Nemati , Scott Robins , Kevin J. Yang
IPC分类号： H01L21/332 , H01L21/337 , H01L21/8238
CPC分类号： G11C11/39 , H01L27/1027 , H01L29/66393 , H01L29/7436
摘要： A thyristor based semiconductor device includes a thyristor having cathode, P-base, N-base and anode regions disposed in electrical series relationship. The N-base region for the thyristor has a cross-section that defines an inverted “T” shape, wherein a buried well in semiconductor material forms is operable as a part of the N-base. The stem to the inverted “T” shape extends from the upper surface of the semiconductor material to the buried well. The P-base region for the thyristor extends laterally outward from a side of the stem that is opposite the anode region of the thyristor, and is further bounded between the buried well and a surface of the semiconductor material. A thinned portion for the N-base is defined between the cathode region of the thyristor and the buried well, and may include supplemental dopant of concentration greater than that for some other portion of the N-base.
摘要翻译：一种基于晶闸管的半导体器件包括具有阴极，P基极，N基极和阳极区域的晶闸管，其以电串联的关系设置。用于晶闸管的N基区域具有限定反向“T”形的横截面，其中半导体材料形式的掩埋阱可操作为N基底的一部分。反向“T”形的杆从半导体材料的上表面延伸到掩埋井。用于晶闸管的P基区域从杆的与晶闸管的阳极区域相对的侧面横向向外延伸，并且进一步限定在掩埋阱和半导体材料的表面之间。在晶闸管的阴极区域和掩埋阱之间限定了用于N-碱的薄化部分，并且可以包括浓度大于N基底的其它部分浓度的补充掺杂剂。

8. 发明授权

US07894256B1 Thyristor based memory cell 失效
标题翻译：基于晶闸管的存储单元
公开(公告)号：US07894256B1
公开(公告)日：2011-02-22
申请号：US11881159
申请日：2007-07-25
申请人： Farid Nemati , Scott Robins , Kevin J. Yang
发明人： Farid Nemati , Scott Robins , Kevin J. Yang
IPC分类号： G11C11/39
CPC分类号： G11C11/39 , H01L27/1027 , H01L29/66393 , H01L29/7436
摘要： A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. The memory cell contains a thyristor body and a gate. The thyristor body has two end region and two base regions, and it is disposed on top of a well. The memory cell is positioned between two isolation regions, and the isolation regions are extended below the well. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.
摘要翻译：新的存储单元仅包含一个晶闸管，而不需要包括一个存取晶体管。可以在体硅晶片上制造包含这些存储单元的存储器阵列。存储单元包含晶闸管体和栅极。晶闸管体具有两个端部区域和两个基极区域，并且它设置在阱的顶部。存储单元位于两个隔离区之间，并且隔离区延伸到阱的下方。第一端区连接到字线，位线和第三线之一。第二端区连接到字线，位线和第三线中的另一端。门连接到字线，位线和第三行的剩余部分。

9. 发明授权

US07894255B1 Thyristor based memory cell 失效
标题翻译：基于晶闸管的存储单元
公开(公告)号：US07894255B1
公开(公告)日：2011-02-22
申请号：US11881049
申请日：2007-07-25
申请人： Farid Nemati , Scott Robins , Kevin J. Yang
发明人： Farid Nemati , Scott Robins , Kevin J. Yang
IPC分类号： G11C11/34
CPC分类号： G11C11/39 , H01L27/1027 , H01L29/66393 , H01L29/7436
摘要： A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. Each memory cell is separated from other memory cells by shallow trench isolation regions. The memory cell comprises a thyristor body and a gate. The thyristor body has two end region and two base regions. The gate is positioned over and insulated from at least a portion of one base region and offset from another base region. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.
摘要翻译：新的存储单元仅包含一个晶闸管，而不需要包括一个存取晶体管。可以在体硅晶片上制造包含这些存储单元的存储器阵列。每个存储单元通过浅沟槽隔离区与其它存储单元分离。存储单元包括可控硅体和栅极。晶闸管体具有两个端部区域和两个基极区域。栅极定位在一个基极区域的至少一部分上并与另一个基极区域偏移绝缘。第一端区连接到字线，位线和第三线之一。第二端区连接到字线，位线和第三线中的另一端。门连接到字线，位线和第三行的剩余部分。

10. 发明授权

US07078739B1 Thyristor-based memory and its method of operation 失效
公开(公告)号：US07078739B1
公开(公告)日：2006-07-18
申请号：US10741539
申请日：2003-12-19
申请人： Farid Nemati , Kevin J. Yang
发明人： Farid Nemati , Kevin J. Yang
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.

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