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1. 发明授权

US07195959B1 Thyristor-based semiconductor device and method of fabrication 失效
标题翻译：基于晶闸管的半导体器件及其制造方法
公开(公告)号：US07195959B1
公开(公告)日：2007-03-27
申请号：US10958820
申请日：2004-10-04
申请人： James D. Plummer , Zachary K. Lee , Kevin J. Yang , Farid Nemati
发明人： James D. Plummer , Zachary K. Lee , Kevin J. Yang , Farid Nemati
IPC分类号： H01L21/332
CPC分类号： H01L29/74 , H01L21/84 , H01L27/1027 , H01L27/1203 , H01L29/66393 , H01L29/7436
摘要： A thyristor-based semiconductor memory device may comprise at least a region thereof, e.g., a p-base region, having high ionization energy impurity, such as a dopant. This high ionization energy impurity within a base region may be operable to compensate for a gain-versus-temperature dependence of a constituent bipolar transistor of the thyristor element of a thyristor-based memory device. In particular embodiments, the high ionization energy impurity may include a donor and/or acceptor in silicon.
摘要翻译：基于晶闸管的半导体存储器件可以至少包括具有高电离能杂质的诸如掺杂剂的区域，例如p基区域。基极区域内的这种高电离能杂质可以用于补偿基于晶闸管的存储器件的晶闸管元件的构成双极晶体管的增益 - 温度依赖性。在具体实施方案中，高电离能杂质可包括硅中的给体和/或受体。

2. 发明授权

US07858449B2 Thyristor device with carbon lifetime adjustment implant and its method of fabrication 失效
标题翻译：具有碳寿命调整植入物的晶闸管器件及其制造方法
公开(公告)号：US07858449B2
公开(公告)日：2010-12-28
申请号：US12367891
申请日：2009-02-09
申请人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
发明人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
IPC分类号： H01L29/72
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
摘要翻译：在制造半导体存储器件的方法中，晶闸管可以形成在半导体材料层中。可以在用于晶闸管的基极 - 发射极结区域中注入和退火碳以影响泄漏特性。因此可以选择碳的密度和/或轰击能量和/或退火，以建立连接的低电压，泄漏特性，基本上大于其没有碳的泄漏。在一个实施例中，注入碳的退火可以与半导体器件的其它注入区域的激活共同进行。

3. 发明授权

US07488626B1 Thyristor device with carbon lifetime adjustment implant and its method of fabrication 失效
标题翻译：具有碳寿命调整植入物的晶闸管器件及其制造方法
公开(公告)号：US07488626B1
公开(公告)日：2009-02-10
申请号：US11483859
申请日：2006-07-10
申请人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
发明人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
IPC分类号： H01L29/72
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
摘要翻译：在制造半导体存储器件的方法中，晶闸管可以形成在半导体材料层中。可以在用于晶闸管的基极 - 发射极结区域中注入和退火碳以影响泄漏特性。因此可以选择碳的密度和/或轰击能量和/或退火，以建立连接的低电压，泄漏特性，基本上大于其没有碳的泄漏。在一个实施例中，注入碳的退火可以与半导体器件的其它注入区域的激活共同进行。

4. 发明授权

US07075122B1 Thyristor device with carbon lifetime adjustment implant and its method of fabrication 失效
公开(公告)号：US07075122B1
公开(公告)日：2006-07-11
申请号：US10670881
申请日：2003-09-25
申请人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
发明人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
IPC分类号： H01L29/72
CPC分类号： H01L27/0817 , H01L29/7436 , H01L29/7455
摘要： In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.

5. 发明申请

US20090162979A1 THYRISTOR DEVICE WITH CARBON LIFETIME ADJUSTMENT IMPLANT AND ITS METHOD OF FABRICATION 失效
标题翻译：具有碳生物调节植入物的制造装置及其制造方法
公开(公告)号：US20090162979A1
公开(公告)日：2009-06-25
申请号：US12367891
申请日：2009-02-09
申请人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
发明人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
IPC分类号： H01L21/266
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
摘要翻译：在制造半导体存储器件的方法中，晶闸管可以形成在半导体材料层中。可以在用于晶闸管的基极 - 发射极结区域中注入和退火碳以影响泄漏特性。因此可以选择碳的密度和/或轰击能量和/或退火，以建立连接的低电压，泄漏特性，基本上大于其没有碳的泄漏。在一个实施例中，注入碳的退火可以与半导体器件的其它注入区域的激活共同进行。

6. 发明授权

US06967358B2 Thyristor-type memory device 失效
标题翻译：晶闸管型存储器件
公开(公告)号：US06967358B2
公开(公告)日：2005-11-22
申请号：US10777453
申请日：2004-02-12
申请人： Farid Nemati , James D. Plummer
发明人： Farid Nemati , James D. Plummer
IPC分类号： G11C11/41 , G11C11/39 , H01L21/8244 , H01L27/06 , H01L27/11 , H01L29/417 , H01L29/423 , H01L29/74 , H01L29/87
CPC分类号： H01L29/74 , G11C11/39 , H01L27/0617 , H01L27/0688 , H01L27/1023 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/41716 , H01L29/42308 , H01L29/749 , H01L29/87
摘要： A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.
摘要翻译：晶闸管器件可用于实现包括高密度存储单元阵列和单个单元电路的各种半导体存储器电路。在一个示例性实施例中，晶闸管器件包括具有相反极性的掺杂区域，以及用于向存储器单元提供读取和写入访问的第一字线。第二字线例如通过增强晶闸管器件从高电导状态到高电导状态的切换而位于与用于写入操作的晶闸管器件的掺杂区域中的一个的绝缘材料相邻并由绝缘材料隔开的位置低电导状态和/或从低电导状态到高电导状态。可以实现这种类型的存储器电路，以显着降低待机功耗和访问时间。

7. 发明授权

US07365373B2 Thyristor-type memory device 失效
标题翻译：晶闸管型存储器件
公开(公告)号：US07365373B2
公开(公告)日：2008-04-29
申请号：US11206627
申请日：2005-08-18
申请人： Farid Nemati , James D. Plummer
发明人： Farid Nemati , James D. Plummer
IPC分类号： H01L29/423
CPC分类号： H01L29/74 , G11C11/39 , H01L27/0617 , H01L27/0688 , H01L27/1023 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/41716 , H01L29/42308 , H01L29/749 , H01L29/87
摘要： A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.
摘要翻译：晶闸管器件可用于实现包括高密度存储单元阵列和单个单元电路的各种半导体存储器电路。在一个示例性实施例中，晶闸管器件包括具有相反极性的掺杂区域，以及用于向存储器单元提供读取和写入访问的第一字线。第二字线例如通过增强晶闸管器件从高电导状态到高电导状态的切换而位于与用于写入操作的晶闸管器件的掺杂区域中的一个的绝缘材料相邻并由绝缘材料隔开的位置低电导状态和/或从低电导状态到高电导状态。可以实现这种类型的存储器电路，以显着降低待机功耗和访问时间。

8. 发明授权

US06448586B1 Semiconductor current-switching device having operational enhancer and method therefor 有权
标题翻译：具有操作增强器的半导体电流开关器件及其方法
公开(公告)号：US06448586B1
公开(公告)日：2002-09-10
申请号：US09666825
申请日：2000-09-21
申请人： Farid Nemati , James D. Plummer
发明人： Farid Nemati , James D. Plummer
IPC分类号： H01L2974
CPC分类号： H01L29/74 , G11C11/39 , H01L27/0617 , H01L27/0688 , H01L27/1023 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/41716 , H01L29/42308 , H01L29/749 , H01L29/87
摘要： A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other type of NDR-based SRAMs.
摘要翻译：可以使用新颖的电容耦合NDR器件来实现各种半导体电路，包括高密度SRAM单元和功率晶闸管结构。在一个示例实施例中，NDR设备用作具有电容耦合门辅助关断和导通机制的薄垂直PNPN结构。基于这种新器件的SRAM在单元面积，待机电流，架构，速度和制造工艺方面相当于相同容量的DRAM。在一个实施例中，基于NDR的SRAM单元仅由两个元件组成，具有8F2封装，可以在高速和低电压下工作，具有良好的噪声余量，并且与主流CMOS的制造工艺兼容。与其他类型的基于NDR的SRAM相比，该单元显着降低了待机功耗。

9. 发明授权

US06727529B2 Semiconductor capacitively-coupled NDR device and related applications in high-density high-speed memories and in power switches 失效
标题翻译：半导体电容耦合NDR器件及相关应用在高密度高速存储器和电源开关中
公开(公告)号：US06727529B2
公开(公告)日：2004-04-27
申请号：US10103241
申请日：2002-03-20
申请人： Farid Nemati , James D. Plummer
发明人： Farid Nemati , James D. Plummer
IPC分类号： H01L2974
CPC分类号： H01L29/74 , G11C11/39 , H01L27/0617 , H01L27/0688 , H01L27/1023 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/41716 , H01L29/42308 , H01L29/749 , H01L29/87
摘要： A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
摘要翻译：可以使用新颖的电容耦合NDR器件来实现各种半导体电路，包括高密度SRAM单元和功率晶闸管结构。在一个示例实施例中，NDR设备用作具有电容耦合门辅助关断和导通机制的薄垂直PNPN结构。基于这种新器件的SRAM在单元面积，待机电流，架构，速度和制造工艺方面相当于相同容量的DRAM。在一个实施例中，基于NDR的SRAM单元仅由两个元件组成，具有8F 2的占位面积，可以在高速和低电压下工作，具有良好的噪声容限，并且与主 - 流CMOS。与其他类型的基于NDR的SRAM相比，该单元显着降低了待机功耗。

10. 发明授权

US06229161B1 Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches 失效
标题翻译：半导体电容耦合NDR器件及其在高密度高速存储器和电源开关中的应用
公开(公告)号：US06229161B1
公开(公告)日：2001-05-08
申请号：US09092449
申请日：1998-06-05
申请人： Farid Nemati , James D. Plummer
发明人： Farid Nemati , James D. Plummer
IPC分类号： H01L2974
CPC分类号： H01L29/74 , G11C11/39 , H01L27/0617 , H01L27/0688 , H01L27/1023 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/41716 , H01L29/42308 , H01L29/749 , H01L29/87
摘要： A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
摘要翻译：可以使用新颖的电容耦合NDR器件来实现各种半导体电路，包括高密度SRAM单元和功率晶闸管结构。在一个示例实施例中，NDR设备用作具有电容耦合门辅助关断和导通机制的薄垂直PNPN结构。基于这种新器件的SRAM在单元面积，待机电流，架构，速度和制造工艺方面相当于相同容量的DRAM。在一个实施例中，基于NDR的SRAM单元仅由两个元件组成，具有8F2封装，可以在高速和低电压下工作，具有良好的噪声余量，并且与主流CMOS的制造工艺兼容。与其他类型的基于NDR的SRAM相比，该单元显着降低了待机功耗。

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