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1. 发明授权

US06455374B1 Method of manufacturing flash memory device 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US06455374B1
公开(公告)日：2002-09-24
申请号：US10026957
申请日：2001-12-27
申请人： Keun Woo Lee , Bong Kil Kim , Ki Jun Kim , Keon Soo Shim
发明人： Keun Woo Lee , Bong Kil Kim , Ki Jun Kim , Keon Soo Shim
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： The present invention relates to a method of manufacturing a flash memory device. According to the present invention, a dielectric film is formed and an amorphous silicon layer is then formed to mitigate a topology generated by patterning of a first polysilicon layer in a cell region. The amorphous silicon layer serves as a protection layer of the dielectric film in the cell region when a gate oxide film in a peripheral circuit region is formed. Therefore, the present invention can not only improve the resistance of a word line in the cell region but also improve the film quality of the dielectric film and the gate oxide film in the peripheral circuit region.
摘要翻译：本发明涉及一种制造闪速存储器件的方法。根据本发明，形成电介质膜，然后形成非晶硅层，以减轻由单元区域中的第一多晶硅层图案化而产生的拓扑。当形成外围电路区域中的栅极氧化膜时，非晶硅层用作电池区域中的电介质膜的保护层。因此，本发明不仅可以提高单元区域中的字线的电阻，而且可以提高外围电路区域中的电介质膜和栅极氧化膜的膜质量。

2. 发明授权

US06743676B2 Method of forming a floating gate in a flash memory device 失效
标题翻译：在闪速存储器件中形成浮动栅极的方法
公开(公告)号：US06743676B2
公开(公告)日：2004-06-01
申请号：US10286980
申请日：2002-11-04
申请人： Sung Kee Park , Ki Seog Kim , Keun Woo Lee , Keon Soo Shim
发明人： Sung Kee Park , Ki Seog Kim , Keun Woo Lee , Keon Soo Shim
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention relates to a method of forming a floating gate in a flash memory device. Upon formation of a device isolation film, a space of a lower polysilicon layer for a floating gate is defined, a bird's beak is formed on an internal surface of a trench by subsequent well sacrificial oxidization process and well oxidization process and an upper polysilicon layer for a floating gate is then formed, so that the space of the floating gate is formed. Therefore, the present invention can reduce the cost since a mask process is not required compared to an existing stepper method and the process cost since a planarization process using chemical mechanical polishing process (CMP) is not required compared to the self-aligned floating mode.
摘要翻译：本发明涉及一种在闪速存储器件中形成浮动栅极的方法。在形成器件隔离膜时，限定用于浮置栅极的下多晶硅层的空间，通过随后的良好牺牲氧化过程和阱氧化过程在沟槽的内表面上形成鸟嘴，以及上部多晶硅层形成浮栅，从而形成浮栅的空间。因此，与现有步进法相比，本发明可以降低成本，因为与自对准浮动模式相比，不需要使用化学机械抛光工艺（CMP）的平坦化处理，因此与现有的步进方法和工艺成本相比不需要掩模处理。

3. 发明申请

US20100235105A1 METHOD FOR ANALYZING DYNAMIC DETECTABLE EVENTS AT THE SINGLE MOLECULE LEVEL 审中-公开
标题翻译：在单分子水平上分析动态检测事件的方法
公开(公告)号：US20100235105A1
公开(公告)日：2010-09-16
申请号：US12686372
申请日：2010-01-12
申请人： Andrei Volkov , Costa M. Colbert , Ivan Pan , Anelia Kraltcheva , Mitsu Reddy , Nasanshargal Battulga , Michael A. Rea , Keun Woo Lee , Susan H. Hardin , Brent Mulder , Chris Hebel , Alok Bandekar
发明人： Andrei Volkov , Costa M. Colbert , Ivan Pan , Anelia Kraltcheva , Mitsu Reddy , Nasanshargal Battulga , Michael A. Rea , Keun Woo Lee , Susan H. Hardin , Brent Mulder , Chris Hebel , Alok Bandekar
IPC分类号： G06F19/00
CPC分类号： C12Q1/6813 , G01N21/6408 , G01N21/6456 , G01N2021/6439
摘要： A method to be implemented on or in a computer is disclosed, where the method includes data collection, calibration, candidate selection, and analysis of data streams associated with each candidate to classify single molecule fluorescence resonance energy transfer events. Once classified, the classification can be related to the nature of the events, such as the identification of dNTP incorporation during primer extension to obtain a base read out of an unknown template.
摘要翻译：公开了一种在计算机上或计算机中实现的方法，其中该方法包括与每个候选物相关联的数据流的数据收集，校准，候选选择和分析，以分类单分子荧光共振能量传递事件。一旦分类，分类可以与事件的性质相关，例如在引物延伸期间鉴定dNTP并入以获得从未知模板读出的碱基。

4. 发明授权

US07095656B2 Method of erasing NAND flash memory device 失效
标题翻译：擦除NAND闪存器件的方法
公开(公告)号：US07095656B2
公开(公告)日：2006-08-22
申请号：US11007183
申请日：2004-12-09
申请人： Keun Woo Lee
发明人： Keun Woo Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Provided is concerned with a method of erasing a NAND flash memory device, capable of restraining an erasing disturbance fail arising from a deselected cell block and improving a product yield of the device by applying a negative voltage to a well of a high voltage transistor forming an X-decoder during an erasing operation in the NAND flash memory device.
摘要翻译：本发明涉及一种擦除NAND闪速存储器件的方法，该方法能够抑制由取消选择的单元块产生的擦除干扰故障，并通过向构成高压晶体管的高电压晶体管的阱施加负电压来提高器件的产品产量 NAND闪存器件中的擦除操作期间的X解码器。

5. 发明授权

US06391665B1 Method of monitoring a source contact in a flash memory 有权
标题翻译：监视闪存中的源触点的方法
公开(公告)号：US06391665B1
公开(公告)日：2002-05-21
申请号：US09722112
申请日：2000-11-27
申请人： Sang Hoan Chang , Ki Seog Kim , Jin Shin , Keun Woo Lee
发明人： Sang Hoan Chang , Ki Seog Kim , Jin Shin , Keun Woo Lee
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , G11C16/04 , G11C29/50 , G11C29/50008 , G11C2029/5006 , H01L21/76895 , H01L27/115
摘要： There is disclosed a method of monitoring a source contact in a flash memory by which whether a source contact having a narrow contact area contacts or not can be easily monitored using over-erase cell characteristic in a flash cell, in a flash memory device in which a source line is formed by a local interconnection method. In the present invention, in order to monitor a contact state at source contacts, the same voltage to the erase condition of a cell is applied to respective terminals (VG terminal, VD terminal, VS terminal and VSS terminal) wherein all the electrons existing at a floating gate in all the cells connected to the VS terminal and VSS terminal become turned on so that they can be over-erased. On the other hands, as electrons existing at the floating gate in two cells shared by any source contacts having a defect contact are not erased, the cells remain turn-off. In this state, if test voltages (VG=0V, VD
摘要翻译：公开了一种监视闪速存储器中的源极触点的方法，通过该闪光存储器中的源极触点可以容易地利用闪存单元中的过擦除单元特性来容易地监视具有窄接触区域的源极触点的触点，源线由本地互连方式形成。在本发明中，为了监测源极触点的接触状态，将与电池的擦除状态相同的电压施加到各个端子（VG端子，VD端子，VS端子和VSS端子），其中所有电子存在于连接到VS端子和VSS端子的所有单元中的浮动栅极变为导通，使得它们可能被过擦除。另一方面，由于存在于由具有缺陷接触的任何源极触点共享的两个电池中的浮动栅极处的电子不被擦除，所以电池保持关断。在这种状态下，如果施加了测试电压（VG = 0V，VD <5V，VS =浮动，VSS =接地），则在具有接触缺陷的部分中，从VD端子到VSS端子的电流断开，从而允许要监控的源触点的接触状态。

6. 发明授权

US5838937A Data transmitting/receiving method using distributed path control in data switching system 失效
标题翻译：在数据交换系统中使用分布式路径控制的数据发送/接收方法
公开(公告)号：US5838937A
公开(公告)日：1998-11-17
申请号：US754091
申请日：1996-11-20
申请人： Hyeun Tae Lee , Keun Woo Lee
发明人： Hyeun Tae Lee , Keun Woo Lee
IPC分类号： H04L12/407 , H04L12/931 , H04L12/933 , H04L12/935 , H04Q11/04 , G06F13/00
CPC分类号： H04L49/30 , H04L49/101 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/13107 , H04Q2213/13174 , H04Q2213/13204
摘要： A data transmitting/receiving method using distributed path control in a data switching system is disclosed, including the steps of: (1) storing data by distributing a first code and a last code of a received data frame, and then reading and storing a frame header; requesting a path setting and then initializing a trial number; transmitting a setup request signal in the next time slot with a destination port address if a polling address is its own address, and thus transmitting the stored header through a data channel when the response signal received from the destination output port indicates an end of the path controlling operation; and transmitting data stored in an input buffer to the end of a frame and requesting a path release at its polling address; (2) releasing the path in case of path release request when the destination port address is its own port address; if the output port is not in use, the output buffer is not is a full state, and a communication channel is available, indicating the end of the path controlling operation in a response bus in case of the path setup request and receiving a switch path setup data to discriminate an initial code and last code of the frame, thereby transmitting the data.
摘要翻译：公开了一种在数据交换系统中使用分布式路径控制的数据发送/接收方法，包括以下步骤：（1）通过分配接收到的数据帧的第一代码和最后一个代码来存储数据，然后读取和存储帧标题请求路径设置，然后初始化试用号码; 如果轮询地址是其自己的地址，则在具有目的地端口地址的下一个时隙中发送建立请求信号，并且当从目的地输出端口接收到的响应信号指示路径的结束时，通过数据信道发送存储的报头控制操作; 以及将存储在输入缓冲器中的数据发送到帧的结尾并请求在其轮询地址处的路径释放; （2）当目的地端口地址是其自己的端口地址时，释放路径释放请求时的路径; 如果输出端口未使用，则输出缓冲器不是完整状态，并且通信信道可用，指示在路径建立请求的情况下在响应总线中路径控制操作的结束并且接收到切换路径设置数据以区分帧的初始码和最后码，从而发送数据。

7. 发明授权

US07848150B2 Flash memory device and method of operating the same 有权
标题翻译：闪存设备及其操作方法
公开(公告)号：US07848150B2
公开(公告)日：2010-12-07
申请号：US12055641
申请日：2008-03-26
申请人： Keun Woo Lee , Ki Seog Kim
发明人： Keun Woo Lee , Ki Seog Kim
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/349
摘要： A flash memory device and a method of operating the same is disclosed, in which the conditions of voltage (or current) applied during the reading operation are differently adjusted according to an accumulated number of times of a programming operation, an erasing operation or a reading operation (an accumulated number of operation cycle). Even if a level of the threshold voltage is changed to a level which differs from that of the target voltage by an increase of the accumulated number of operation cycle regardless of the programming operation (or the erasing operation) being normally performed, the reliability of the reading operation can be enhanced to prevent a malfunction of the memory cell from being generated.
摘要翻译：公开了一种闪速存储装置及其操作方法，其中根据编程操作，擦除操作或读取的累积次数，不同地调整在读取操作期间施加的电压（或电流）的条件操作（累计操作周期数）。即使通过正常执行编程操作（或擦除操作），通过累积操作周期数的增加，阈值电压的电平变化到与目标电压的电平不同的电平，则可靠性可以增强读取操作以防止生成存储器单元的故障。

8. 发明授权

US07696577B2 Memory cell array in a semiconductor memory device with select lines formed in a U-like shape 失效
标题翻译：具有形成为U形形状的选择线的半导体存储器件中的存储单元阵列
公开(公告)号：US07696577B2
公开(公告)日：2010-04-13
申请号：US11771146
申请日：2007-06-29
申请人： Keun Woo Lee
发明人： Keun Woo Lee
IPC分类号： H01L27/105
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521
摘要： A memory cell array in a semiconductor device includes a semiconductor substrate having active areas and isolation areas in parallel, a plurality of select lines having generally a U like shape and is configured to cross over the active areas and the isolation areas, and a plurality of word lines formed between the select lines. In view of the select line being formed in U like shape, an occurrence of a punch through phenomenon is prevented by a junction area formed between the select lines. As a result, a margin for reducing a width of the select line is increased.
摘要翻译：半导体器件中的存储单元阵列包括具有活动区域和隔离区域的半导体衬底，多个选择线具有大致U形形状并且被配置为跨越有源区域和隔离区域，并且多个在选择行之间形成的字线。鉴于选择线形成为U形形状，通过形成在选择线之间的接合区域来防止穿孔现象的发生。结果，增加了用于减小选择线的宽度的余量。

9. 发明授权

US07668697B2 Method for analyzing dynamic detectable events at the single molecule level 有权
标题翻译：分析单分子水平动态可检测事件的方法
公开(公告)号：US07668697B2
公开(公告)日：2010-02-23
申请号：US11671956
申请日：2007-02-06
申请人： Andrei Volkov , Costa M. Colbert , Ivan Pan , Anelia Kraltcheva , Mitsu Reddy , Nasanshargal Battulga , Michael A. Rea , Keun Woo Lee , Susan H. Hardin , Brent Mulder , Chris Hebel , Alok Bandekar
发明人： Andrei Volkov , Costa M. Colbert , Ivan Pan , Anelia Kraltcheva , Mitsu Reddy , Nasanshargal Battulga , Michael A. Rea , Keun Woo Lee , Susan H. Hardin , Brent Mulder , Chris Hebel , Alok Bandekar
IPC分类号： G06F19/00 , G06F17/40 , G01N33/00
CPC分类号： C12Q1/6813 , G01N21/6408 , G01N21/6456 , G01N2021/6439
摘要： A method to be implemented on or in a computer is disclosed, where the method includes data collection, calibration, candidate selection, and analysis of data streams associated with each candidate to classify single molecule fluorescence resonance energy transfer events. Once classified, the classification can be related to the nature of the events, such as the identification of dNTP incorporation during primer extension to obtain a base read out of an unknown template.
摘要翻译：公开了一种在计算机上或计算机中实现的方法，其中该方法包括与每个候选物相关联的数据流的数据收集，校准，候选选择和分析，以分类单分子荧光共振能量传递事件。一旦分类，分类可以与事件的性质相关，例如在引物延伸期间鉴定dNTP并入以获得从未知模板读出的碱基。

10. 发明授权

US07391663B2 Structure and method for measuring the channel boosting voltage of NAND flash memory at a node between drain/source select transistor and adjacent flash memory cell 有权
标题翻译：用于测量漏极/源极选择晶体管与相邻闪存单元之间节点处NAND闪存的通道升压电压的结构和方法
公开(公告)号：US07391663B2
公开(公告)日：2008-06-24
申请号：US11307515
申请日：2006-02-10
申请人： Keun Woo Lee
发明人： Keun Woo Lee
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/50 , G11C16/04 , G11C16/0483 , G11C16/3418 , G11C16/3454 , G11C29/02 , G11C29/1201 , G11C29/50004 , G11C2029/1204 , G11C2029/5004
摘要： Provided is a structure for testing a NAND flash memory including a string select transistor, a source select transistor, flash memory cells connected in series between the string select transistor and a source select transistor and a measurement pad coupled to a node between a flash memory cell and the string select transistor or the source select transistor.
摘要翻译：提供了一种用于测试NAND闪存的结构，包括串选择晶体管，源选择晶体管，串联连接在串选择晶体管和源选择晶体管之间的闪存单元和耦合到闪存单元之间的节点的测量垫和串选择晶体管或源选择晶体管。

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