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1. 发明授权

US07008856B2 Method for fabricating AND-type flash memory cell 失效
标题翻译：制造AND型闪存单元的方法
公开(公告)号：US07008856B2
公开(公告)日：2006-03-07
申请号：US10750250
申请日：2003-12-31
申请人： Chang Hun Han , Bong Kil Kim
发明人： Chang Hun Han , Bong Kil Kim
IPC分类号： H01L21/76
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , Y10S438/95
摘要： A flash memory cell and fabrication method thereof are disclosed. An example fabrication method deposits a pad oxide layer and a pad nitride layer on a semiconductor substrate, patterns the pad nitride layer, implants ions into the substrate to form an ion implant region, forms spacers on sidewalls of the pad nitride layer pattern, removes some part of the pad oxide layer and the top portion of the substrate through an etching process using the spacers as a mask to form a trench that divides the ion implant region into two parts. The example fabrication method also forms a gap filling insulating layer over the resulting substrate, and forms a trench isolation layer and junction regions simultaneously by removing the spacers, the pad nitride layer pattern, the pad oxide layer, and the top portion of the gap filling insulating layer.
摘要翻译：公开了闪存单元及其制造方法。示例性制造方法将衬垫氧化物层和衬垫氮化物层沉积在半导体衬底上，将衬垫氮化物层，衬底离子注入衬底以形成离子注入区域，在衬垫氮化物层图案的侧壁上形成间隔物，去除一些通过使用间隔物作为掩模的蚀刻工艺，形成将离子注入区域分成两部分的沟槽的衬垫氧化物层的一部分和衬底的顶部。示例性制造方法还在所得到的衬底上形成间隙填充绝缘层，并且通过去除间隔物，衬垫氮化物层图案，衬垫氧化物层和间隙填充物的顶部部分同时形成沟槽隔离层和接合区域绝缘层。

2. 发明授权

US06472752B1 Flash memory device 有权
标题翻译：闪存设备
公开(公告)号：US06472752B1
公开(公告)日：2002-10-29
申请号：US09717032
申请日：2000-11-22
申请人： Bong Kil Kim , Sung Mun Jung
发明人： Bong Kil Kim , Sung Mun Jung
IPC分类号： H01L2348
CPC分类号： H01L27/105
摘要： A flash memory device is configured to address the problems that charges generated when via hole is etched is charged to a junction region through a metal line and are thus concentrated on a tunnel oxide film, thus making distribution of a threshold voltage over a cell uneven when a device is driven. In order to solve the problems, the device has a junction region in an outside circuit region so charges generated when via hole is etched is concentrated on the junction region formed in the outside circuit region. Thus, it can prevent concentration of the charges on the cell and thus make uniform distribution of the threshold voltage over a cell array.
摘要翻译：闪存器件被配置为解决当通孔被蚀刻时产生的电荷通过金属线被充电到结区域并因此集中在隧道氧化物膜上的问题，从而使阈值电压在电池上的分布不均匀，一个设备被驱动。为了解决上述问题，该器件在外部电路区域具有接合区域，因此当通孔被蚀刻时产生的电荷集中在形成在外部电路区域中的接合区域上。因此，可以防止电池在电池上的集中，从而使电池阵列上的阈值电压均匀分布。

3. 发明授权

US07906387B2 Method for manufacturing a transistor 有权
标题翻译：制造晶体管的方法
公开(公告)号：US07906387B2
公开(公告)日：2011-03-15
申请号：US12269021
申请日：2008-11-11
申请人： Bong Kil Kim
发明人： Bong Kil Kim
IPC分类号： H01L21/8238
CPC分类号： H01L29/665 , H01L29/66568 , H01L29/7833
摘要： A method for manufacturing a transistor is disclosed, which is capable of improving matching characteristics of regions within a transistor or among transistors on a wafer, from wafer-to-wafer, or from lot-to-lot. The method includes forming a photoresist pattern on a semiconductor substrate including an isolation layer, forming a drift region by implanting first and second dopant ions using the photoresist pattern as a mask, forming a gate oxide layer on the semiconductor substrate, forming a poly gate on the gate oxide layer, forming source and drain regions a predetermined distance from the poly gate, and forming a silicide layer on the above structure.
摘要翻译：公开了一种用于制造晶体管的方法，其能够改善晶片内部的区域或晶片之间的晶体管，晶圆到晶片或批次之间的匹配特性。该方法包括在包括隔离层的半导体衬底上形成光致抗蚀剂图案，通过使用光致抗蚀剂图案作为掩模注入第一和第二掺杂剂离子形成漂移区，在半导体衬底上形成栅极氧化层，形成多晶硅栅极栅极氧化层，与多晶硅栅极形成预定距离的源极和漏极区域，并在上述结构上形成硅化物层。

4. 发明申请

US20060160253A1 Method and apparatus for wafer temperature regulation 审中-公开
标题翻译：晶圆温度调节方法和装置
公开(公告)号：US20060160253A1
公开(公告)日：2006-07-20
申请号：US11332315
申请日：2006-01-17
申请人： Bong-Kil Kim , Dae-Ho Go , Yun-Jung Moon
发明人： Bong-Kil Kim , Dae-Ho Go , Yun-Jung Moon
IPC分类号： H01L21/66 , H01L21/02
CPC分类号： H01L21/67109
摘要： A method and apparatus for regulating the temperature a wafer is provided. The apparatus may include a temperature controlling unit provided within the chamber and regulating the temperature of the wafer; a wafer support pin for adjusting the position of the wafer with respect to the temperature controlling unit; and/or a positioning assembly for adjusting the wafer support pin by which the position of the wafer is controlled. The temperature of a wafer baked at a high temperature may be regulated by performing a series of temperature controlling operation in order to reduce the possibility of fracturing the wafer due to a change in temperature.
摘要翻译：一种用于调节晶片温度的方法和装置。设备可以包括设置在室内并调节晶片的温度的温度控制单元; 用于调节晶片相对于温度控制单元的位置的晶片支撑销; 和/或用于调节晶片支撑销的定位组件，由此控制晶片的位置。可以通过进行一系列温度控制操作来调节在高温下烘烤的晶片的温度，以便降低由于温度变化导致晶片压裂的可能性。

5. 发明授权

US07632732B2 Method of manufacturing MOS transistor 失效
标题翻译：制造MOS晶体管的方法
公开(公告)号：US07632732B2
公开(公告)日：2009-12-15
申请号：US12344551
申请日：2008-12-28
申请人： Bong-Kil Kim
发明人： Bong-Kil Kim
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/82385 , H01L21/823892 , H01L27/0928
摘要： A method of manufacturing a transistor may include: forming a first well over a silicon substrate; forming a first mask pattern over the silicon substrate and using the formed first mask pattern to form a second well; removing the first mask pattern; forming a second mask pattern over the silicon substrate and using the formed second mask pattern to form a first drift region; removing the second mask pattern; forming a third mask pattern and using the formed third mask pattern to form a second drift region; removing the third mask pattern; forming a field oxide film over the silicon substrate; and introducing first conductive impurity ions into an upper surface of the silicon substrate by channel ion implantation.
摘要翻译：制造晶体管的方法可以包括：在硅衬底上形成第一阱; 在所述硅衬底上形成第一掩模图案并使用所形成的第一掩模图案形成第二阱; 去除第一掩模图案; 在所述硅衬底上形成第二掩模图案，并使用所形成的第二掩模图案形成第一漂移区域; 去除第二掩模图案; 形成第三掩模图案并使用所形成的第三掩模图案形成第二漂移区域; 去除第三掩模图案; 在硅衬底上形成场氧化膜; 并且通过沟道离子注入将第一导电杂质离子引入硅衬底的上表面。

6. 发明申请

US20090166737A1 Method for Manufacturing a Transistor 有权
标题翻译：晶体管制造方法
公开(公告)号：US20090166737A1
公开(公告)日：2009-07-02
申请号：US12269021
申请日：2008-11-11
申请人： Bong Kil KIM
发明人： Bong Kil KIM
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/665 , H01L29/66568 , H01L29/7833
摘要： A method for manufacturing a transistor is disclosed, which is capable of improving matching characteristics of regions within a transistor or among transistors on a wafer, from wafer-to-wafer, or from lot-to-lot. The method includes forming a photoresist pattern on a semiconductor substrate including an isolation layer, forming a drift region by implanting first and second dopant ions using the photoresist pattern as a mask, forming a gate oxide layer on the semiconductor substrate, forming a poly gate on the gate oxide layer, forming source and drain regions a predetermined distance from the poly gate, and forming a silicide layer on the above structure.
摘要翻译：公开了一种用于制造晶体管的方法，其能够改善晶片内部的区域或晶片之间的晶体管，晶圆到晶片或批次之间的匹配特性。该方法包括在包括隔离层的半导体衬底上形成光致抗蚀剂图案，通过使用光致抗蚀剂图案作为掩模注入第一和第二掺杂剂离子形成漂移区，在半导体衬底上形成栅极氧化层，形成多晶硅栅极栅极氧化层，与多晶硅栅极形成预定距离的源极和漏极区域，并在上述结构上形成硅化物层。

7. 发明申请

US20090166719A1 LDMOS SEMICONDUCTOR DEVICE MASK 审中-公开
标题翻译： LDMOS半导体器件掩模
公开(公告)号：US20090166719A1
公开(公告)日：2009-07-02
申请号：US12344555
申请日：2008-12-28
申请人： Bong-Kil Kim
发明人： Bong-Kil Kim
IPC分类号： H01L29/78 , H01L29/423 , H01L21/336
CPC分类号： H01L21/26513 , H01L21/266 , H01L21/823814 , H01L27/0928 , H01L29/0653 , H01L29/78
摘要： Embodiments relate to an LDMOS semiconductor device mask that may reduce current leakage under a gate-off condition. According to embodiments, an LDMOS semiconductor device mask may include a moat mask to define a moat region, an NDT mask to define an N drift region, a PDT mask to define a P drift region, and a gate mask to form a gate. According to embodiments, a PDT mask may be configured to expose a field region of a semiconductor device.
摘要翻译： LDMOS半导体器件掩模的实施例涉及可以减少栅极截止条件下的电流泄漏。根据实施例，LDMOS半导体器件掩模可以包括用于限定护环区域的护城河掩模，用于限定N漂移区域的NDT掩模，用于限定P漂移区域的PDT掩模和用于形成栅极的栅极掩模。根据实施例，PDT掩模可以被配置为暴露半导体器件的场区域。

8. 发明授权

US07432157B2 Method of fabricating flash memory 失效
标题翻译：制造闪存的方法
公开(公告)号：US07432157B2
公开(公告)日：2008-10-07
申请号：US10950218
申请日：2004-09-24
申请人： Bong Kil Kim
发明人： Bong Kil Kim
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： Flash memory and methods of fabricating flash memory are disclosed. A disclosed method comprises: forming a first floating gate; and extending the first floating gate by forming a second floating gate adjacent a first sidewall of the floating gate. The second floating gate extends upward above the first floating gate. The method also includes depositing a dielectric layer on the first floating gate and the second floating gate; and forming a control gate on the dielectric layer.
摘要翻译：公开了闪速存储器和制造闪速存储器的方法。所公开的方法包括：形成第一浮动栅极; 以及通过在所述浮动栅极的第一侧壁附近形成第二浮动栅极来延伸所述第一浮置栅极。第二浮栅在第一浮栅上方向上延伸。该方法还包括在第一浮动栅极和第二浮动栅极上沉积介电层; 以及在所述电介质层上形成控制栅极。

9. 发明授权

US06455374B1 Method of manufacturing flash memory device 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US06455374B1
公开(公告)日：2002-09-24
申请号：US10026957
申请日：2001-12-27
申请人： Keun Woo Lee , Bong Kil Kim , Ki Jun Kim , Keon Soo Shim
发明人： Keun Woo Lee , Bong Kil Kim , Ki Jun Kim , Keon Soo Shim
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： The present invention relates to a method of manufacturing a flash memory device. According to the present invention, a dielectric film is formed and an amorphous silicon layer is then formed to mitigate a topology generated by patterning of a first polysilicon layer in a cell region. The amorphous silicon layer serves as a protection layer of the dielectric film in the cell region when a gate oxide film in a peripheral circuit region is formed. Therefore, the present invention can not only improve the resistance of a word line in the cell region but also improve the film quality of the dielectric film and the gate oxide film in the peripheral circuit region.
摘要翻译：本发明涉及一种制造闪速存储器件的方法。根据本发明，形成电介质膜，然后形成非晶硅层，以减轻由单元区域中的第一多晶硅层图案化而产生的拓扑。当形成外围电路区域中的栅极氧化膜时，非晶硅层用作电池区域中的电介质膜的保护层。因此，本发明不仅可以提高单元区域中的字线的电阻，而且可以提高外围电路区域中的电介质膜和栅极氧化膜的膜质量。

10. 发明申请

US20090011588A1 Flash Memory and Methods of Fabricating Flash Memory 审中-公开
标题翻译：闪存和闪存制造方法
公开(公告)号：US20090011588A1
公开(公告)日：2009-01-08
申请号：US12202163
申请日：2008-08-29
申请人： BONG KIL KIM
发明人： BONG KIL KIM
IPC分类号： H01L21/28
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/40114 , H01L29/42324 , H01L29/66825
摘要： Flash memory and methods of fabricating flash memory are disclosed. A disclosed method comprises: forming a first floating gate; and extending the first floating gate by forming a second floating gate adjacent a first sidewall of the floating gate. The second floating gate extends upward above the first floating gate. The method also includes depositing a dielectric layer on the first floating gate and the second floating gate; and forming a control gate on the dielectric layer.
摘要翻译：公开了闪速存储器和制造闪速存储器的方法。所公开的方法包括：形成第一浮动栅极; 以及通过在所述浮动栅极的第一侧壁附近形成第二浮动栅极来延伸所述第一浮置栅极。第二浮栅在第一浮栅上方向上延伸。该方法还包括在第一浮动栅极和第二浮动栅极上沉积介电层; 以及在所述电介质层上形成控制栅极。

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