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1. 发明申请

US20110177670A1 THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION 有权
标题翻译：通过硅胶通过光刻对准和注册
公开(公告)号：US20110177670A1
公开(公告)日：2011-07-21
申请号：US12690299
申请日：2010-01-20
申请人： Russell T. Herrin , Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Russell T. Herrin , Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01L21/71
CPC分类号： H01L21/76898 , G03F9/7076 , G03F9/708 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing an integrated circuit structure forms a first opening in a substrate and lines the first opening with a protective liner. The method deposits a material into the first opening and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. The method removes the material from the first opening through the second opening in the protective material. The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.
摘要翻译：一种制造集成电路结构的方法在衬底中形成第一开口并且用保护性衬垫对第一开口进行排列。该方法将材料沉积到第一开口中并在基底上形成保护材料。保护材料包括工艺控制标记，并且包括在第一开口上方并对准第二开口的第二开口。该方法通过保护材料中的第二开口从第一开口移除材料。过程控制标记包括在保护材料内的仅部分延伸穿过保护材料的凹槽，使得在过程控制标记之下的基底的部分不受去除材料的过程的影响。

2. 发明授权

US08039356B2 Through silicon via lithographic alignment and registration 有权
标题翻译：通过硅片通过光刻对准和配准
公开(公告)号：US08039356B2
公开(公告)日：2011-10-18
申请号：US12690299
申请日：2010-01-20
申请人： Russell T. Herrin , Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Russell T. Herrin , Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01L21/76
CPC分类号： H01L21/76898 , G03F9/7076 , G03F9/708 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing an integrated circuit structure forms a first opening in a substrate and lines the first opening with a protective liner. The method deposits a material into the first opening and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. The method removes the material from the first opening through the second opening in the protective material. The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.
摘要翻译：一种制造集成电路结构的方法在衬底中形成第一开口并且用保护性衬垫对第一开口进行排列。该方法将材料沉积到第一开口中并在基底上形成保护材料。保护材料包括工艺控制标记，并且包括在第一开口上方并对准第二开口的第二开口。该方法通过保护材料中的第二开口从第一开口移除材料。过程控制标记包括在保护材料内的仅部分延伸穿过保护材料的凹槽，使得在过程控制标记之下的基底的部分不受去除材料的过程的影响。

3. 发明申请

US20110177435A1 Photomasks having sub-lithographic features to prevent undesired wafer patterning 审中-公开
标题翻译：具有亚光刻特征以防止不期望的晶片图案化的光掩模
公开(公告)号：US20110177435A1
公开(公告)日：2011-07-21
申请号：US12690312
申请日：2010-01-20
申请人： Russell T. Herrin , Edmund J. Sprogis , Anthony K. Stamper
发明人： Russell T. Herrin , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： G03F1/00
CPC分类号： G03F1/42 , G03F1/36 , G03F1/38
摘要： A photomask that is used as a light filter in an exposure system is made of at least one layer of material comprising one or more transparent regions and one or more non-transparent regions. The difference between the transparent regions and the non-transparent regions defines the features that will be illuminated by the exposure system on a photoresist that will be exposed using the exposure system. The features comprise one or more device shapes and at least one sub-lithographic shape that will be exposed upon the photoresist. The sub-lithographic shape has an sub-lithographic shape size that is limited in such a way that the sub-lithographic shape causes a physical change only in a surface of the photoresist. Therefore, because the sub-lithographic shape is so small, it avoids forming an opening through the photoresist after the photoresist is developed and only causes a change on the surface of the photoresist.
摘要翻译：在曝光系统中用作滤光器的光掩模由包括一个或多个透明区域和一个或多个不透明区域的至少一层材料制成。透明区域和不透明区域之间的差异限定了曝光系统将在将使用曝光系统曝光的光刻胶上照亮的特征。这些特征包括一个或多个器件形状和将被暴露在光刻胶上的至少一个亚光刻形状。亚光刻形状具有亚光刻形状尺寸，其受到限制，使得亚光刻形状仅在光致抗蚀剂的表面引起物理变化。因此，由于亚光刻形状如此之小，因此避免了在光致抗蚀剂显影之后通过光致抗蚀剂形成开口，并且仅引起光致抗蚀剂表面的变化。

4. 发明授权

US08631570B2 Through wafer vias with dishing correction methods 有权
标题翻译：通过具有凹陷校正方法的晶片通孔
公开(公告)号：US08631570B2
公开(公告)日：2014-01-21
申请号：US13369414
申请日：2012-02-09
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01K3/10 , H05K3/02 , H05K3/10 , H01L29/40
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.
摘要翻译：提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

5. 发明申请

US20120137515A1 THROUGH WAFER VIAS WITH DISHING CORRECTION METHODS 有权
标题翻译：通过具有循环校正方法的WAVER VIAS
公开(公告)号：US20120137515A1
公开(公告)日：2012-06-07
申请号：US13369414
申请日：2012-02-09
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01K3/10
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.
摘要翻译：提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

6. 发明授权

US08166651B2 Through wafer vias with dishing correction methods 有权
标题翻译：通过具有凹陷校正方法的晶片通孔
公开(公告)号：US08166651B2
公开(公告)日：2012-05-01
申请号：US12181359
申请日：2008-07-29
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01K3/10 , H05K3/02 , H05K3/10 , H01L29/40
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a through wafer via including forming the through wafer via (TWV) into a substrate and through a first dielectric layer over the substrate; planarizing the first dielectric layer using a chemical mechanical polish before forming a second dielectric layer; forming the second dielectric layer over the substrate and the TWV; forming at least one first contact through the second dielectric layer and to the TWV; forming at least one second contact through the second dielectric layer and the first dielectric layer directly and electrically connected to another structure upon the substrate; and forming a first metal wiring layer directly over the second dielectric layer, the first metal wiring layer directly and physically contacting the at least one first contact and the at least one second contact.
摘要翻译：一种形成贯穿晶片通孔的方法，包括通过（TWV）形成贯穿晶片进入衬底并穿过衬底上的第一介电层; 在形成第二电介质层之前，使用化学机械抛光平面化第一介电层; 在所述衬底和所述TWV上形成所述第二电介质层; 通过所述第二介电层和所述TWV形成至少一个第一接触; 通过所述第二电介质层和所述第一介电层形成至少一个第二接触，并且在所述衬底上直接电连接到另一结构; 以及直接在所述第二电介质层上方形成第一金属布线层，所述第一金属布线层直接地和物理地接触所述至少一个第一触点和所述至少一个第二触点。

7. 发明授权

US08136084B2 Arranging through silicon vias in IC layout 有权
标题翻译：在IC布局中排列硅通孔
公开(公告)号：US08136084B2
公开(公告)日：2012-03-13
申请号：US12555981
申请日：2009-09-09
申请人： Donald R. Dean, Jr. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
发明人： Donald R. Dean, Jr. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： G06F17/52
CPC分类号： H01L21/76898 , G06F17/5072
摘要： A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage.
摘要翻译：评估包括多个贯穿硅通孔（TSV）的IC布局的一部分以识别线性对准的TSV。修改IC布局的部分以减少多个线性对齐的TSV，导致较少的晶片断裂。

8. 发明申请

US20110057319A1 ARRANGING THROUGH SILICON VIAS IN IC LAYOUT 有权
标题翻译：通过IC布局中的硅胶排列
公开(公告)号：US20110057319A1
公开(公告)日：2011-03-10
申请号：US12555981
申请日：2009-09-09
申请人： Donald R. Dean, JR. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
发明人： Donald R. Dean, JR. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01L23/48 , G06F17/50
CPC分类号： H01L21/76898 , G06F17/5072
摘要： A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage.
摘要翻译：评估包括多个贯穿硅通孔（TSV）的IC布局的一部分以识别线性对准的TSV。修改IC布局的部分以减少多个线性对齐的TSV，导致较少的晶片断裂。

9. 发明申请

US20100025857A1 IC CHIP AND DESIGN STRUCTURE WITH THROUGH WAFER VIAS DISHING CORRECTION 有权
标题翻译：通过WAVER VIAS DISHING CORRECTION进行IC芯片和设计结构
公开(公告)号：US20100025857A1
公开(公告)日：2010-02-04
申请号：US12181467
申请日：2008-07-29
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01L23/48 , G06F9/45
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684
摘要： An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV; and a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting the TWV contact.
摘要翻译：具有TWV触点的IC芯片和设计结构接触TWV并延伸穿过TWV上的第二介电层。 IC芯片可以包括基板; 穿过至少一个第一电介质层并进入衬底的贯通晶片通孔（TWV）; TWV触点接触TWV并延伸穿过TWV上的第二电介质层; 以及在所述第二电介质层上的第一金属布线层，所述第一金属布线层与所述TWV触点接触。

10. 发明授权

US07859114B2 IC chip and design structure with through wafer vias dishing correction 有权
标题翻译： IC芯片和设计结构通过晶圆过孔进行修正
公开(公告)号：US07859114B2
公开(公告)日：2010-12-28
申请号：US12181467
申请日：2008-07-29
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L29/06 , H01L23/053 , H01L23/12
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684
摘要： An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV; and a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting the TWV contact.
摘要翻译：具有TWV触点的IC芯片和设计结构接触TWV并延伸穿过TWV上的第二介电层。 IC芯片可以包括基板; 穿过至少一个第一电介质层并进入衬底的贯通晶片通孔（TWV）; TWV触点接触TWV并延伸穿过TWV上的第二电介质层; 以及在所述第二电介质层上的第一金属布线层，所述第一金属布线层与所述TWV触点接触。

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