专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08914764B2 Adaptive workload based optimizations coupled with a heterogeneous current-aware baseline design to mitigate current delivery limitations in integrated circuits 有权
标题翻译：基于自适应工作负载的优化与异构电流感知基线设计相结合，以减轻集成电路中的当前传输限制
公开(公告)号：US08914764B2
公开(公告)日：2014-12-16
申请号：US13526252
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译：与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。设计辅助工具用于根据当前的交付要求在整个芯片上分配C4。该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

2. 发明申请

US20140195996A1 ADAPTIVE WORKLOAD BASED OPTIMIZATIONS COUPLED WITH A HETEROGENEOUS CURRENT-AWARE BASELINE DESIGN TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS 有权
标题翻译：基于自适应工作负载的优化与异构电流基准设计相结合，以减轻集成电路中的电流传输限制
公开(公告)号：US20140195996A1
公开(公告)日：2014-07-10
申请号：US13526252
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译：与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。设计辅助工具用于根据当前交付要求在整个芯片上分配C4。该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

3. 发明申请

US20140082574A1 Token-Based Current Control to Mitigate Current Delivery Limitations in Integrated Circuits 有权
标题翻译：基于令牌的电流控制，以缓解集成电路中的当前传输限制
公开(公告)号：US20140082574A1
公开(公告)日：2014-03-20
申请号：US13526153
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F9/455 , G06F9/46 , G06F9/5044 , G06F15/177 , G06F17/5022 , G06F17/5045 , G06F2212/1041 , G06F2217/78
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译：与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。设计辅助工具用于根据当前交付要求在整个芯片上分配C4。该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

4. 发明授权

US07493586B2 Method and system product for implementing uncertainty in integrated circuit designs with programmable logic 失效
标题翻译：用可编程逻辑实现集成电路设计中的不确定性的方法和系统产品
公开(公告)号：US07493586B2
公开(公告)日：2009-02-17
申请号：US11553076
申请日：2006-10-26
申请人： John A Darringer , George W Doerre , Victor N Kravets
发明人： John A Darringer , George W Doerre , Victor N Kravets
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed is a method, system and computer program product to specify an integrated circuit. The integrated circuit includes a hardwired specific logic technology portion and a programmable specific logic technology portion. The method includes generating a hybrid logic network by mapping each uncertain logic function to an abstract programmable logic element implementation thereof and by mapping each known logic function to a technology-independent logic element implementation thereof; simplifying the hybrid logic network using logic synthesis optimizations; mapping the simplified hybrid logic network to a specific technology by mapping the abstract programmable logic element implementation to the specific programmable logic technology and the technology-independent logic element implementation to the specific logic technology; and further includes optimizing the mapped network to meet performance constraints. Generating involves using integrated circuit specification language extensions that include an Uncertain Function that is used in place of a logic function or operator, an Uncertain Function Assertion for imposing at least one constraint on the Uncertain Function, an Uncertain Register for a register having a programmable size within a specified range and an Uncertain Constant.
摘要翻译：公开了一种用于指定集成电路的方法，系统和计算机程序产品。集成电路包括硬连线专用逻辑技术部分和可编程特定逻辑技术部分。该方法包括通过将每个不确定逻辑函数映射到其抽象可编程逻辑元件实现并通过将每个已知逻辑功能映射到与技术无关的逻辑元件实现来生成混合逻辑网络; 使用逻辑综合优化简化混合逻辑网络; 通过将抽象可编程逻辑元件实现映射到特定可编程逻辑技术和与技术无关的逻辑元件实现到特定逻辑技术，将简化的混合逻辑网络映射到特定技术; 并且还包括优化映射网络以满足性能约束。生成涉及使用集成电路规范语言扩展，包括用于代替逻辑功能或运算符的不确定函数，用于对不确定函数施加至少一个约束的不确定函数断言，具有可编程大小的寄存器的不确定寄存器在指定范围内和不确定常数。

5. 发明授权

US07089542B2 Method and apparatus for finding errors in software programs using satisfiability of constraints 失效
标题翻译：使用约束可满足性在软件程序中发现错误的方法和装置
公开(公告)号：US07089542B2
公开(公告)日：2006-08-08
申请号：US10318823
申请日：2002-12-13
申请人： Daniel Brand , John A. Darringer , Florian Krohm
发明人： Daniel Brand , John A. Darringer , Florian Krohm
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F11/3608
摘要： A method and apparatus are provided for analyzing software programs. The invention combines data flow analysis and symbolic execution with a new constraint solver to create a more efficient and accurate static software analysis tool. The disclosed constraint solver combines rewrite rules with arithmetic constraint solving to provide a constraint solver that is efficient, flexible and capable of satisfactorily expressing semantics and handling arithmetic constraints. The disclosed constraint solver comprises a number of data structures to remember existing range, equivalence and inequality constraints and incrementally add new constraints. The constraint solver returns an inconsistent indication only if the range constraints, equivalence constraints, and inequality constraints are mutually inconsistent.
摘要翻译：提供了一种用于分析软件程序的方法和装置。本发明将数据流分析和符号执行与新的约束求解器相结合，以创建更有效和准确的静态软件分析工具。所公开的约束求解器将重写规则与算术约束求解相结合，以提供有效，灵活且能够令人满意地表达语义和处理算术约束的约束求解器。所公开的约束求解器包括许多数据结构，以记住现有的范围，等价和不等式约束，并逐渐增加新的约束。只有当范围约束，等价约束和不等式约束相互不一致时，约束求解器才会返回不一致的指示。

6. 发明授权

US4703435A Logic Synthesizer 失效
标题翻译：逻辑合成器
公开(公告)号：US4703435A
公开(公告)日：1987-10-27
申请号：US631364
申请日：1984-07-16
申请人： John A. Darringer , William H. Joyner, Jr.
发明人： John A. Darringer , William H. Joyner, Jr.
IPC分类号： G06F17/50 , G06F7/00 , G06F15/60
CPC分类号： G06F17/505
摘要： Logic is synthesized from a flowchart-level description by first generating an AND/OR logic design, simplifying the AND/OR logic, converting the AND/OR logic to NAND or NOR logic, applying particular sequences of simplifying transformations to the NAND or NOR logic, converting the simplified NAND or NOR logic to a target technology, and simplifying the target technology where possible. The end result is an interconnection of primitives of the target technology in a language from which automated logic diagrams can be produced.
摘要翻译：通过首先产生与/或逻辑设计，简化AND / OR逻辑，将AND / OR逻辑转换为NAND或NOR逻辑，将简化变换的特定序列应用于NAND或NOR逻辑，从流程图级描述合成逻辑，将简化的NAND或NOR逻辑转换为目标技术，并尽可能简化目标技术。最终的结果是以可以产生自动化逻辑图的语言将目标技术的原语互连。

7. 发明申请

US20130339762A1 ADAPTIVE WORKLOAD BASED OPTIMIZATIONS TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS 有权
标题翻译：基于自适应工作负载的优化，以减轻集成电路中的当前交付限制
公开(公告)号：US20130339762A1
公开(公告)日：2013-12-19
申请号：US13526230
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F1/26 , G06F9/46 , H03K3/00
CPC分类号： H01L23/00 , G06F11/00 , G06F11/3062 , H01L23/50 , H01L25/065 , H01L2224/16145 , H01L2224/16225
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译：与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发节流机制（包括基于令牌的节流），以限制每个C4的当前传输超过预先 - 建立的限制或期限。设计辅助工具用于根据当前交付要求在整个芯片上分配C4。该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

8. 发明授权

US07131098B2 Computer program product for implementing uncertainty in integrated circuit designs with programmable logic 失效
标题翻译：用于实现具有可编程逻辑的集成电路设计中的不确定性的计算机程序产品
公开(公告)号：US07131098B2
公开(公告)日：2006-10-31
申请号：US10714750
申请日：2003-11-17
申请人： John A Darringer , George W Doerre , Victor N Kravets
发明人： John A Darringer , George W Doerre , Victor N Kravets
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed is a method, system and computer program product to specify an integrated circuit. The integrated circuit includes a hardwired specific logic technology portion and a programmable specific logic technology portion. The method includes generating a hybrid logic network by mapping each uncertain logic function to an abstract programmable logic element implementation thereof and by mapping each known logic function to a technology-independent logic element implementation thereof; simplifying the hybrid logic network using logic synthesis optimizations; mapping the simplified hybrid logic network to a specific technology by mapping the abstract programmable logic element implementation to the specific programmable logic technology and the technology-independent logic element implementation to the specific logic technology; and further includes optimizing the mapped network to meet performance constraints. Generating involves using integrated circuit specification language extensions that include an Uncertain Function that is used in place of a logic function or operator, an Uncertain Function Assertion for imposing at least one constraint on the Uncertain Function, an Uncertain Register for a register having a programmable size within a specified range and an Uncertain Constant.
摘要翻译：公开了一种用于指定集成电路的方法，系统和计算机程序产品。集成电路包括硬连线专用逻辑技术部分和可编程特定逻辑技术部分。该方法包括通过将每个不确定逻辑函数映射到其抽象可编程逻辑元件实现并通过将每个已知逻辑功能映射到与技术无关的逻辑元件实现来生成混合逻辑网络; 使用逻辑综合优化简化混合逻辑网络; 通过将抽象可编程逻辑元件实现映射到特定可编程逻辑技术和与技术无关的逻辑元件实现到特定逻辑技术，将简化的混合逻辑网络映射到特定技术; 并且还包括优化映射网络以满足性能约束。生成涉及使用集成电路规范语言扩展，包括用于代替逻辑功能或运算符的不确定函数，用于对不确定函数施加至少一个约束的不确定函数断言，具有可编程大小的寄存器的不确定寄存器在指定范围内和不确定常数。

9. 发明授权

US08863068B2 Current-aware floorplanning to overcome current delivery limitations in integrated circuits 有权
标题翻译：电流识别布局规划，以克服集成电路中的当前传输限制
公开(公告)号：US08863068B2
公开(公告)日：2014-10-14
申请号：US13526194
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/50 , G06F2217/78
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译：与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。设计辅助工具用于根据当前交付要求在整个芯片上分配C4。该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

10. 发明授权

US08826216B2 Token-based current control to mitigate current delivery limitations in integrated circuits 有权
标题翻译：基于令牌的电流控制，以减轻集成电路中的当前传输限制
公开(公告)号：US08826216B2
公开(公告)日：2014-09-02
申请号：US13526153
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F17/50 , G06F9/44 , G06F9/46 , G06F15/177 , G06F9/00 , G06F1/24 , G06F9/50 , G06F9/455
CPC分类号： G06F17/5054 , G06F9/455 , G06F9/46 , G06F9/5044 , G06F15/177 , G06F17/5022 , G06F17/5045 , G06F2212/1041 , G06F2217/78
摘要： A system and method of operating an integrated circuit (IC) having a fixed layout of one or more blocks having one or more current sources therein that draw electrical current from a power source. The method includes dynamically issuing to a block configured to perform operations responsive to an instruction received at the block, a reserve amount of tokens; determining for each issuance of instruction to the block whether that block's reserve token amount exceeds zero; and one of: issuing the instruction to the block if the token reserve for that block is greater than one, and decrementing, after issuance of the instruction, by one token the block's reserve token amount, or, preventing issuance of an instruction to the block. In the method, each block may be initialized to have: a reserve token amount of zero, a token expiration period; a token generation cycle and a token generation amount.
摘要翻译：一种具有固定布局的集成电路（IC）的系统和方法，所述集成电路（IC）具有一个或多个具有一个或多个电流源的块，其中所述一个或多个块来自电源。所述方法包括动态地发布到被配置为响应于在所述块处接收的指令执行操作的块，标记的保留量; 确定每个向块的指令的发出是否该块的储备标记量超过零; 其中之一是：如果该块的令牌保留大于1，则向块发出指令，并且在发出指令之后递减一个令牌块的保留令牌量，或者阻止向块发出指令。在该方法中，每个块可以被初始化为具有：保留令牌量为零，令牌到期期间; 令牌生成周期和令牌生成量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式