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1. 发明授权

US08640075B2 Early design cycle optimzation 失效
标题翻译：早期设计周期优化
公开(公告)号：US08640075B2
公开(公告)日：2014-01-28
申请号：US13486177
申请日：2012-06-01
申请人： Charles Jay Alpert , Robert M. Averill, III , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
发明人： Charles Jay Alpert , Robert M. Averill, III , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
摘要翻译：一些示例性实施例包括用于设计集成电路的计算机实现的方法。计算机实现的方法包括接收集成电路的分层网络设计，其中分层设计包括耦合在一起的多个组件。计算机实现的方法包括基于包括缺失断言，一个或多个缺失锁存器，源驱动程序中的至少一个的问题，检测组件数量的组件具有故障定时和不完整定时中的至少一个输入源电压大于源极限极限阈值，以及具有大于漏极极限极限阈值的输入接收器的接收器。计算机实现的方法包括使用独立于问题的不同组件替换组件，并且基于不同的组件测试组件数量的其他组件。

2. 发明申请

US20130326450A1 EARLY DESIGN CYCLE OPTIMZATION 失效
标题翻译：早期设计周期优化
公开(公告)号：US20130326450A1
公开(公告)日：2013-12-05
申请号：US13486177
申请日：2012-06-01
申请人： Charles Jay Alpert , Robert M. Averill , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
发明人： Charles Jay Alpert , Robert M. Averill , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
摘要翻译：一些示例性实施例包括用于设计集成电路的计算机实现的方法。计算机实现的方法包括接收集成电路的分层网络设计，其中分层设计包括耦合在一起的多个组件。计算机实现的方法包括基于包括缺失断言，一个或多个缺失锁存器，源驱动程序中的至少一个的问题，检测组件数量的组件具有故障定时和不完整定时中的至少一个输入源电压大于源极限极限阈值，以及具有大于漏极极限极限阈值的输入接收器的接收器。计算机实现的方法包括使用独立于问题的不同组件替换组件，并且基于不同的组件测试组件数量的其他组件。

3. 发明授权

US08365120B2 Resolving global coupling timing and slew violations for buffer-dominated designs 有权
标题翻译：解决以缓冲区为主的设计的全局耦合时序和回滚冲突
公开(公告)号：US08365120B2
公开(公告)日：2013-01-29
申请号：US12959029
申请日：2010-12-02
申请人： Charles J. Alpert , Joachim G. Clabes , Zhuo Li , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Joachim G. Clabes , Zhuo Li , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/84
摘要： A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is routable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated.
摘要翻译：提供了一种机制，用于在集成电路（IC）设计中解决提升或耦合时序问题和转换冲突，而不会牺牲延迟模式时序。响应于针对新IC设计中的多个网络中的每个网络而接收的用于生成新的IC设计的请求，确定网络是否可以通过使用成本函数的多个小区中的小区可路由与电池相关联，使得与网络相关联的耦合电容等于或低于预定的耦合电容阈值。响应于网络能够通过耦合电容等于或低于门限路由到小区，网络被分配给小区内的至少一个轨道。对于正在路由的新IC设计中的所有网络，生成新的IC设计。

4. 发明申请

US20120144358A1 Resolving Global Coupling Timing and Slew Violations for Buffer-Dominated Designs 有权
标题翻译：解决缓冲区主导设计的全局耦合时序和摆动违例
公开(公告)号：US20120144358A1
公开(公告)日：2012-06-07
申请号：US12959029
申请日：2010-12-02
申请人： Charles J. Alpert , Clabes G. Joachim , Zhuo Li , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Clabes G. Joachim , Zhuo Li , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/84
摘要： A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is rentable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated.
摘要翻译：提供了一种机制，用于在集成电路（IC）设计中解决提升或耦合时序问题和转换冲突，而不会牺牲延迟模式时序。响应于针对新IC设计中的多个网络中的每个网络而接收的用于生成新的IC设计的请求，确定网络是否可以通过使用成本函数的多个小区中的小区可租借与电池相关联，使得与网络相关联的耦合电容等于或低于预定的耦合电容阈值。响应于网络能够通过耦合电容等于或低于门限路由到小区，网络被分配给小区内的至少一个轨道。对于正在路由的新IC设计中的所有网络，生成新的IC设计。

5. 发明授权

US07895557B2 Concurrent buffering and layer assignment in integrated circuit layout 有权
标题翻译：集成电路布局中的并行缓冲和层分配
公开(公告)号：US07895557B2
公开(公告)日：2011-02-22
申请号：US12100477
申请日：2008-04-10
申请人： Charles J. Alpert , Zhuo Li , Tuhin Mahmud , Stephen T. Quay , Paul G. Villarrubla
发明人： Charles J. Alpert , Zhuo Li , Tuhin Mahmud , Stephen T. Quay , Paul G. Villarrubla
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5045 , G06F17/505
摘要： A method and system for concurrent buffering and layer assignment in integrated current layout. Buffers are inserted and metal interconnects or “wires” are sized for every net, which consists of one driver and one or more receivers, such that timing skew constraints can be met. Long nets are promoted to a higher level if the slew violation can be fixed only by a promotion of the net or if the “slack” gain available by this promotion is equal to or greater than a predesignated layer of promotion threshold. In response to determining these layer assignments, the method and system then systematically demotes nets that are not critical and which do not impact the circuit and electrical constraints in order to minimize the use of high layer wire resources.
摘要翻译：一种集成电流布局中并发缓存和层分配的方法和系统。插入缓冲器，并且每个网络的金属互连或“电线”的大小适合于由一个驱动器和一个或多个接收器组成的网络，从而可以满足定时偏移约束。如果可以通过网络的推广来修复浪费的违规行为，或者如果该促销活动可用的“松弛”收益等于或大于预先指定的促销门槛层，长网将被提升到更高的水平。响应于确定这些层分配，该方法和系统然后系统地降低不关键且不影响电路和电气约束的网，以便最小化高层线材资源的使用。

6. 发明申请

US20090013299A1 BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS 审中-公开
标题翻译：缓冲插入减少VLSI电路中的WIRELENGTH
公开(公告)号：US20090013299A1
公开(公告)日：2009-01-08
申请号：US12207498
申请日：2008-09-10
申请人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F2217/84
摘要： Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.
摘要翻译：集成电路设计网络中的线长通过形成要互连的接收集群，在每个集群中插入缓冲区并通过将一个集群的接收器连接到另一个集群的缓冲区来提供集群之间的分支连接来减少，以创建一个跨越所有水槽的缓冲树。缓冲区被插入到最靠近网络源的簇的相应边界框上的点处。提供与另一个群集的缓冲区的分支连接的宿是与该缓冲区最接近的宿（除了群集中的那些宿）。可以通过用不同的边界框检查不同对的汇，并且将其边界框中具有最小半周的对中的一个作为聚类的最佳对来形成群集。

7. 发明申请

US20070271543A1 Buffer Insertion to Reduce Wirelength in VLSI Circuits 有权
标题翻译：缓冲插入以减少VLSI电路中的线长度
公开(公告)号：US20070271543A1
公开(公告)日：2007-11-22
申请号：US11383544
申请日：2006-05-16
申请人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F2217/84
摘要： Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.
摘要翻译：集成电路设计网络中的线长通过形成要互连的接收集群，在每个集群中插入缓冲区并通过将一个集群的接收器连接到另一个集群的缓冲区来提供集群之间的分支连接来减少，以创建一个跨越所有水槽的缓冲树。缓冲区被插入到最靠近网络源的簇的相应边界框上的点处。提供与另一个群集的缓冲区的分支连接的宿是与该缓冲区最接近的宿（除了群集中的那些宿）。可以通过用不同的边界框检查不同对的汇，并且将其边界框中具有最小半周的对中的一个作为聚类的最佳对来形成群集。

8. 发明授权

US07484199B2 Buffer insertion to reduce wirelength in VLSI circuits 有权
标题翻译：缓冲器插入以减少VLSI电路中的电线长度
公开(公告)号：US07484199B2
公开(公告)日：2009-01-27
申请号：US11383544
申请日：2006-05-16
申请人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F2217/84
摘要： Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.
摘要翻译：集成电路设计网络中的线长通过形成要互连的接收集群，在每个集群中插入缓冲区并通过将一个集群的接收器连接到另一个集群的缓冲区来提供集群之间的分支连接来减少，以创建一个跨越所有水槽的缓冲树。缓冲区被插入到最靠近网络源的簇的相应边界框上的点处。提供与另一个群集的缓冲区的分支连接的宿是与该缓冲区最接近的宿（除了群集中的那些宿）。可以通过用不同的边界框检查不同对的汇，并且将其边界框中具有最小半周的对中的一个作为聚类的最佳对来形成群集。

9. 发明授权

US07448007B2 Slew constrained minimum cost buffering 有权
标题翻译：压缩约束最低成本缓冲
公开(公告)号：US07448007B2
公开(公告)日：2008-11-04
申请号：US11457495
申请日：2006-07-14
申请人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.
摘要翻译：缓冲插入技术解决了压摆约束，同时最大限度地减少了缓冲区成本。该方法构建了汇的初始解决方案，每个都具有相关的成本，压摆和电容。当解决方案向源传播时，将线电容和线压力加到解决方案中。当选择缓冲器进行可能的插入时，将解决方案的电压设置为零，同时根据所选择的缓冲器增加解决方案的成本，并将电容设置为缓冲器的固有电容。通过增加分支电容和成本，并选择最高的分支电压，合并两条相交线分支的解决方案。解决方案集通过忽略具有大于压摆约束的转矩分量的解决方案来更新，并且消除由另一解决方案主导的任何解决方案。选择具有最小成本的解决方案作为最终解决方案。

10. 发明申请

US20080016479A1 Slew Constrained Minimum Cost Buffering 有权
标题翻译：压缩约束最小成本缓冲
公开(公告)号：US20080016479A1
公开(公告)日：2008-01-17
申请号：US11457495
申请日：2006-07-14
申请人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew arc added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.
摘要翻译：缓冲插入技术解决了压摆约束，同时最大限度地减少了缓冲区成本。该方法构建了汇的初始解决方案，每个都具有相关的成本，压摆和电容。当解决方案向源传播时，将线电容和电线电弧加到溶液中。当选择缓冲器进行可能的插入时，将解决方案的电压设置为零，同时根据所选择的缓冲器增加解决方案的成本，并将电容设置为缓冲器的固有电容。通过增加分支电容和成本，并选择最高的分支电压，合并两条相交线分支的解决方案。解决方案集通过忽略具有大于压摆约束的转矩分量的解决方案来更新，并且消除由另一解决方案主导的任何解决方案。选择具有最小成本的解决方案作为最终解决方案。

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