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1. 发明申请

US20090153324A1 DESIGN STRUCTURE FOR MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT 失效
标题翻译：在集成电路中测量功耗的设计结构
公开(公告)号：US20090153324A1
公开(公告)日：2009-06-18
申请号：US12046501
申请日：2008-03-12
申请人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
发明人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
IPC分类号： G08B21/00
CPC分类号： G01R31/31721
摘要： An design structure for measuring power consumed during operation of an integrated circuit. The design structure including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal.
摘要翻译：一种用于测量集成电路运行期间消耗的功率的设计结构。该设计结构包括：具有输入和输出的数据处理电路，所述数据处理电路被配置为基于输入数据信号产生输出数据信号; 功率测量电路，被配置为测量由所述输入信号产生所述输出信号时由所述处理电路消耗的电力量;连接在所述处理电路和所述处理电路的电源之间的所述功率测量电路; 以及存储元件，被配置为存储包含表示由处理电路消耗的电力量的值的标签，用于从输入数据信号生成输出数据信号，以及（a）输入数据信号的输入数据或（b ）指向输入数据信号的输入数据的指针。

2. 发明授权

US07715995B2 Design structure for measurement of power consumption within an integrated circuit 失效
标题翻译：集成电路内功耗测量的设计结构
公开(公告)号：US07715995B2
公开(公告)日：2010-05-11
申请号：US12046501
申请日：2008-03-12
申请人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
发明人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
IPC分类号： G06F19/00
CPC分类号： G01R31/31721
摘要： An design structure for measuring power consumed during operation of an integrated circuit. The design structure including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal.
摘要翻译：一种用于测量集成电路运行期间消耗的功率的设计结构。该设计结构包括：具有输入和输出的数据处理电路，所述数据处理电路被配置为基于输入数据信号产生输出数据信号; 功率测量电路，被配置为测量由所述输入信号产生所述输出信号时由所述处理电路消耗的电力量;连接在所述处理电路和所述处理电路的电源之间的功率测量电路; 以及存储元件，被配置为存储包含表示由处理电路消耗的电力量的值的标签，用于从输入数据信号生成输出数据信号，以及（a）输入数据信号的输入数据或（b ）指向输入数据信号的输入数据的指针。

3. 发明申请

US20090157334A1 MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：在集成电路中测量功耗
公开(公告)号：US20090157334A1
公开(公告)日：2009-06-18
申请号：US11956836
申请日：2007-12-14
申请人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
发明人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
IPC分类号： G06F19/00 , G01R21/00
CPC分类号： H03K19/0008 , G01R31/318575
摘要： An apparatus and method for measuring power consumed during operation of an integrated circuit. The apparatus including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal.
摘要翻译：一种用于测量集成电路操作期间消耗的功率的装置和方法。该装置包括：具有输入和输出的数据处理电路，该数据处理电路被配置为基于输入数据信号产生一个输出数据信号; 功率测量电路，被配置为测量由所述输入信号产生所述输出信号时由所述处理电路消耗的电力量;连接在所述处理电路和所述处理电路的电源之间的功率测量电路; 以及存储元件，被配置为存储包含表示由处理电路消耗的电力量的值的标签，用于从输入数据信号生成输出数据信号，以及（a）输入数据信号的输入数据或（b ）指向输入数据信号的输入数据的指针。

4. 发明授权

US07831935B2 Method and architecture for power management of an electronic device 有权
标题翻译：电子设备电源管理的方法和架构
公开(公告)号：US07831935B2
公开(公告)日：2010-11-09
申请号：US11846578
申请日：2007-08-29
申请人： Kerry Bernstein , Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Keith Robert Williams , Sebastian Theodore Ventrone
发明人： Kerry Bernstein , Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Keith Robert Williams , Sebastian Theodore Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F1/3203 , G06F1/3287 , H01L25/16 , H01L28/60 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/19105 , Y02D10/171 , H01L2224/0401
摘要： A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between the local power grid and the local ground grid; a global storage capacitor coupling a global power grid to a global ground grid, each local ground grid connected to the global ground grid; one or more switches, each switch selectively connecting the global power grid to a single and different corresponding local power grid; and a power dispatch unit adapted to open and close the one or more switches.
摘要翻译：一种降低低功率电子设备中的静态功耗的方法。所述电子设备包括一个或多个功率岛，每个功率岛包括：将本地电网耦合到本地接地网的局部存储电容器; 以及连接在本地电网与本地接地网之间的功能电路; 将全球电网耦合到全球接地网的全球存储电容器，每个局部地电网连接到全球接地网; 一个或多个开关，每个开关选择性地将全局电网连接到单个和不同的相应的局部电网; 以及适于打开和关闭所述一个或多个开关的电力调度单元。

5. 发明授权

US07454642B2 Method and architecture for power management of an electronic device 有权
标题翻译：电子设备电源管理的方法和架构
公开(公告)号：US07454642B2
公开(公告)日：2008-11-18
申请号：US11278262
申请日：2006-03-31
申请人： Kerry Bernstein , Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Keith Robert Williams , Sebastian Theodore Ventrone
发明人： Kerry Bernstein , Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Keith Robert Williams , Sebastian Theodore Ventrone
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , H01L25/16 , H01L28/60 , H01L2224/16225 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105 , Y02D10/171 , Y10T307/391
摘要： A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between the local power grid and the local ground grid; a global storage capacitor coupling a global power grid to a global ground grid, each local ground grid connected to the global ground grid; one or more switches, each switch selectively connecting the global power grid to a single and different corresponding local power grid; and a power dispatch unit adapted to open and close the one or more switches.
摘要翻译：一种降低低功率电子设备中的静态功耗的方法。所述电子设备包括一个或多个功率岛，每个功率岛包括：将本地电网耦合到本地接地网的局部存储电容器; 以及连接在本地电网与本地接地网之间的功能电路; 将全球电网耦合到全球接地网的全球存储电容器，每个局部地电网连接到全球接地网; 一个或多个开关，每个开关选择性地将全局电网连接到单个和不同的相应的局部电网; 以及适于打开和关闭所述一个或多个开关的电力调度单元。

6. 发明授权

US6026471A Anticipating cache memory loader and method 失效
标题翻译：预测缓存内存加载器和方法
公开(公告)号：US6026471A
公开(公告)日：2000-02-15
申请号：US751468
申请日：1996-11-19
申请人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Wilbur David Pricer , Sebastian Theodore Ventrone
发明人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Wilbur David Pricer , Sebastian Theodore Ventrone
IPC分类号： G06F9/46 , G06F12/08 , G06F12/10 , G06F17/12
CPC分类号： G06F12/0862 , G06F9/461 , G06F2212/6024
摘要： According to the present invention, an anticipating cache memory loader is provided to "pre-load" the cache with the data and instructions most likely to be needed by the CPU once the currently executing task is completed or interrupted. The data and instructions most likely to be needed after the currently executing task is completed or executed is the same data and instructions that were loaded into the cache at the time the next scheduled task was last preempted or interrupted. By creating and storing an index to the contents of the cache for various tasks at the point in time the tasks are interrupted, the data and instructions previously swapped out of the cache can be retrieved from main memory and restored to the cache when needed. By using available bandwidth to pre-load the cache for the next scheduled task, the CPU can begin processing the next scheduled task more quickly and efficiently than if the present invention were not utilized. Using the present invention, CPU stalls will be reduced because the CPU will operate more efficiently without waiting for excessive periods of time for the cache to be loaded with relevant data and instructions.
摘要翻译：根据本发明，提供一种预期的高速缓存存储器加载器，用于在当前执行的任务完成或中断之后，用CPU最有可能需要的数据和指令来“预加载”高速缓存。在完成或执行当前执行任务之后最可能需要的数据和指令是在下一个计划任务最后被抢占或中断时加载到缓存中的相同数据和指令。通过在任务中断的时间点为各种任务创建和存储索引到高速缓存的内容，可以从主存储器中检索先前从高速缓存交换的数据和指令，并在需要时将其还原到高速缓存。通过使用可用带宽来预加载用于下一个计划任务的高速缓存，与不利用本发明相比，CPU可以更快速和有效地开始处理下一个计划的任务。使用本发明，CPU停止将被减少，因为CPU将更有效地操作而不用等待超时间段来缓存相关数据和指令。

7. 发明授权

US5918246A Apparatus and method for prefetching data based on information contained in a compiler generated program map 失效
标题翻译：基于编译器生成的程序映射中包含的信息来预取数据的装置和方法
公开(公告)号：US5918246A
公开(公告)日：1999-06-29
申请号：US788870
申请日：1997-01-23
申请人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Wilbur David Pricer , Sebastian Theodore Ventrone
发明人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Wilbur David Pricer , Sebastian Theodore Ventrone
IPC分类号： G06F9/45 , G06F12/08 , G06F12/00 , G06F9/38 , G06F13/00
CPC分类号： G06F8/4442 , G06F12/0862 , G06F2212/6028
摘要： An apparatus and method for pre-loading a cache memory based on information contained in a compiler generated program map are disclosed. The program map is generated by the compiler at the time source code is compiled into object code. For each application program, the user would have this program map stored with the object file. At the beginning of the program execution cycle, the operating system will determine whether or not a program map exists for the application. If a program map exists, the operating system will load the program map into an area of RAM designated as the program map random access memory (RAM). The program map will be used to pre-load the cache with the appropriate data and instructions for the central processing unit (CPU) to process. The program mapping would be the address location of each jump/branch target that the CPU might encounter during the execution cycle. Each of these locations represent a starting point for a new code sequence. At the start of the map will be an identifier field to mark the start of the map. The next field in the program map will provide the entry point of the starting address of the application program. If a particular application program does not have a program map, the program and cache operation will remain unchanged. This feature provides backwards compatibility with existing application programs.
摘要翻译：公开了一种基于编译器生成的程序映射中包含的信息来预加载高速缓冲存储器的装置和方法。程序地图由编译器在源代码被编译成目标代码时生成。对于每个应用程序，用户将该目录文件存储该程序映射。在程序执行周期开始时，操作系统将确定应用程序是否存在程序映射。如果存在程序映射，则操作系统将程序映射加载到指定为程序映射随机存取存储器（RAM）的RAM区域中。程序地图将用于预先加载高速缓存，并具有相应的数据和指令，供中央处理单元（CPU）处理。程序映射将是执行周期中CPU可能遇到的每个跳转/转移目标的地址位置。这些位置中的每一个代表新代码序列的起始点。在地图的开始，将是一个标识符字段来标记地图的开始。程序地图中的下一个字段将提供应用程序起始地址的入口点。如果特定的应用程序没有程序映射，程序和缓存操作将保持不变。此功能提供与现有应用程序的向后兼容性。

8. 发明申请

US20080183941A1 HARDWARE ASSISTED BUS STATE TRANSITION USING CONTENT ADDRESSABLE MEMORIES. 审中-公开
标题翻译：硬件辅助总线状态转换使用内容可寻址的记忆。
公开(公告)号：US20080183941A1
公开(公告)日：2008-07-31
申请号：US11627588
申请日：2007-01-26
申请人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
IPC分类号： G06F3/00
CPC分类号： G06F13/4059
摘要： A universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.
摘要翻译：集成电路（IC）上的通用外围处理器架构包括与配置为状态机的第一和第二三进制内容可寻址存储器（TCAM）设备通信的第一数据总线和第二数据总线。第一和第二处理器耦合到第一总线接口逻辑和第二总线接口逻辑。第一和第二数据存储设备与第一和第二处理器进行通信，并且耦合到第一和第二数据总线并彼此通信。 TCAM设备被配置为状态机，并且使用预定义的协议耦合到并适于与处理器，数据存储设备和总线接口逻辑的接口。

9. 发明授权

US08347019B2 Structure for hardware assisted bus state transition circuit using content addressable memories 失效
标题翻译：使用内容可寻址存储器的硬件辅助总线状态转换电路的结构
公开(公告)号：US08347019B2
公开(公告)日：2013-01-01
申请号：US12122321
申请日：2008-05-16
申请人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/4059
摘要： A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.
摘要翻译：包括集成电路（IC）上的通用外围处理器架构的设计结构包括与配置为状态机的第一和第二三进制内容可寻址存储器（TCAM）设备通信的第一数据总线和第二数据总线。第一和第二处理器耦合到第一总线接口逻辑和第二总线接口逻辑。第一和第二数据存储设备与第一和第二处理器进行通信，并且耦合到第一和第二数据总线并彼此通信。 TCAM设备被配置为状态机，并且使用预定义的协议耦合到并适于与处理器，数据存储设备和总线接口逻辑的接口。

10. 发明申请

US20080282015A1 DESIGN STRUCTURE FOR HARDWARE ASSISTED BUS STATE TRANSITION CIRCUIT USING CONTENT ADDRESSABLE MEMORIES 失效
标题翻译：硬件辅助总线转换电路使用内部可寻址存储器的设计结构
公开(公告)号：US20080282015A1
公开(公告)日：2008-11-13
申请号：US12122321
申请日：2008-05-16
申请人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
IPC分类号： G06F13/40
CPC分类号： G06F13/4059
摘要： A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.
摘要翻译：包括集成电路（IC）上的通用外围处理器架构的设计结构包括与配置为状态机的第一和第二三进制内容可寻址存储器（TCAM）设备通信的第一数据总线和第二数据总线。第一和第二处理器耦合到第一总线接口逻辑和第二总线接口逻辑。第一和第二数据存储设备与第一和第二处理器进行通信，并且耦合到第一和第二数据总线并彼此通信。 TCAM设备被配置为状态机，并且使用预定义的协议耦合到并适于与处理器，数据存储设备和总线接口逻辑的接口。

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