专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070162792A1 METHOD FOR INCREASING THE MANUFACTURING YIELD OF PROGRAMMABLE LOGIC DEVICES 失效
标题翻译：增加可编程逻辑器件制造工艺的方法
公开(公告)号：US20070162792A1
公开(公告)日：2007-07-12
申请号：US11275536
申请日：2006-01-12
申请人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Sebastian Ventrone , Paul Zuchowski
发明人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Sebastian Ventrone , Paul Zuchowski
IPC分类号： G01R31/26 , G11C29/00
CPC分类号： G01R31/31718 , G11C17/14 , G11C29/88 , H03K19/17764 , H03K19/17796
摘要： A method for increasing the manufacturing yield of field programmable gate arrays (FPGAS) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.
摘要翻译：一种提高现场可编程门阵列（FPGAS）或其他可编程逻辑器件（PLD）的制造成品率的方法。 FPGA或其他PLD形成在几个部分中，每个部分都有自己的电源总线和输入/输出连接。测试FPGA或其他PLD的每个部分，以识别FPGA或其他PLD中的缺陷。 FPGA或其他PLD根据该部分是否具有可接受的缺陷数量进行排序。为FPGA或其他PLD芯片或部件分配的唯一编号将其识别为部分良好。用于执行和配置FPGA或其他PLD的软件可以使用唯一编号仅对FPGA或其他PLD的已识别功能部分进行编程。结果是产量增加，部分好的FPGA或其他PLD仍然可以被利用。

2. 发明申请

US20080030226A1 FPGA POWERUP TO KNOWN FUNCTIONAL STATE 失效
标题翻译： FPGA电源到已知的功能状态
公开(公告)号：US20080030226A1
公开(公告)日：2008-02-07
申请号：US11869921
申请日：2007-10-10
申请人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
发明人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
IPC分类号： H03K19/173
CPC分类号： H03K19/17776 , H03K19/17732 , H03K19/17756 , H03K19/17772
摘要： A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.
摘要翻译：包括非基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）设备。非基于非编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而在上电时节省宝贵的处理时间。公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和冲洗和扫描电路。还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。

3. 发明申请

US20050251778A1 System and method for dynamically executing a function in a programmable logic array 有权
标题翻译：用于在可编程逻辑阵列中动态执行功能的系统和方法
公开(公告)号：US20050251778A1
公开(公告)日：2005-11-10
申请号：US11181053
申请日：2005-07-14
申请人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone
发明人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone
IPC分类号： G06F15/78 , H03K19/177 , H03K19/00
CPC分类号： H03K19/17752 , G06F15/7867 , H03K19/17756 , H03K19/1776
摘要： A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB 1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.
摘要翻译：一种可重构逻辑阵列（RLA）系统（104），包括RLA（108）和编程器（112），用于循环地重新编程RLA。需要比RLA中包含的逻辑大的功能（F）被划分为多个功能块（FB 1，FB 2，FB 3）。程序员包含将RLA分割成位于两个存储区域SR 1，SR 2之间的功能区域FR的软件（144）。然后，程序员用功能块的功能块顺序地对功能区进行编程，使得功能块在存储区之间交替地进行处理。当编程器用下一个功能块重新配置功能区域并且重新配置存储区域之一以接收下一个功能块的输出时，从当前功能块传递到下一个功能块的数据被保存在另一个存储区域中。

4. 发明申请

US20070198808A1 PROCESSOR PIPELINE ARCHITECTURE LOGIC STATE RETENTION SYSTEMS AND METHODS 有权
标题翻译：处理器管道结构逻辑状态保持系统和方法
公开(公告)号：US20070198808A1
公开(公告)日：2007-08-23
申请号：US11276236
申请日：2006-02-20
申请人： Kerry Bernstein , Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Sebastian Ventrone , Keith Williams
发明人： Kerry Bernstein , Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Sebastian Ventrone , Keith Williams
IPC分类号： G06F15/00
CPC分类号： G06F9/3869 , G11C27/026
摘要： A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.
摘要翻译：公开了一种用于保持处理器流水线架构的逻辑状态的系统，方法和程序产品。比较器位于处理器流水线架构的两个阶段之间。存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。提供了与早期输出值相同的参考逻辑。逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点处产生逻辑，该逻辑是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态电容器。提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

5. 发明申请

US20050120323A1 Method for modifying the behavior of a state machine 失效
标题翻译：修改状态机行为的方法
公开(公告)号：US20050120323A1
公开(公告)日：2005-06-02
申请号：US10725712
申请日：2003-12-02
申请人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone
发明人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： G06F17/5054
摘要： A method and system for modifying the function of a state machine having a programmable logic device. The method including: (a) modifying a high-level design of the state machine to obtain a modified high-level design of the state machine with a modified function; (b) generating a programmable logic device netlist from differences in the high-level design and the modified design; and (c) installing the modified function into the state machine by programming the programmable logic device based on the programmable logic device netlist.
摘要翻译：一种用于修改具有可编程逻辑器件的状态机的功能的方法和系统。该方法包括：（a）修改状态机的高级设计，以获得具有修改功能的状态机修改后的高级设计; （b）从高级设计和改进设计的差异中产生可编程逻辑器件网表; 和（c）通过基于可编程逻辑器件网表对可编程逻辑器件进行编程来将修改后的功能安装到状态机中。

6. 发明申请

US20070075733A1 FPGA POWERUP TO KNOWN FUNCTIONAL STATE 有权
标题翻译： FPGA电源到已知的功能状态
公开(公告)号：US20070075733A1
公开(公告)日：2007-04-05
申请号：US11162997
申请日：2005-09-30
申请人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
发明人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
IPC分类号： H03K19/177
CPC分类号： H03K19/17776 , H03K19/17732 , H03K19/17756 , H03K19/17772
摘要： A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.
摘要翻译：包括基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）装置。非基于编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而节省加电时的处理时间。公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和齐平扫描电路。还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。

7. 发明申请

US20050077917A1 SYSTEM AND METHOD FOR DYNAMICALLY EXECUTING A FUNCTION IN A PROGRAMMABLE LOGIC ARRAY 失效
标题翻译：在可编程逻辑阵列中动态执行功能的系统和方法
公开(公告)号：US20050077917A1
公开(公告)日：2005-04-14
申请号：US10605603
申请日：2003-10-13
申请人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone
发明人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone
IPC分类号： G06F15/78 , H03K19/177
CPC分类号： H03K19/17752 , G06F15/7867 , H03K19/17756 , H03K19/1776
摘要： A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is re-configuring function region with the next functional block and re-configuring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.
摘要翻译：一种可重构逻辑阵列（RLA）系统（104），包括RLA（108）和编程器（112），用于循环地重新编程RLA。需要比RLA中包含的逻辑大的功能（F）被划分为多个功能块（FB1，FB2，FB3）。程序员包含将RLA分割成位于两个存储区域SR1，SR2之间的功能区域FR的软件（144）。然后，程序员用功能块的功能块顺序地对功能区进行编程，使得功能块在存储区之间交替地进行处理。当程序员使用下一个功能块重新配置功能区域并且重新配置用于接收下一个功能块的输出的一个存储区域时，从当前功能块传递到下一个功能块的数据被保存在其他存储区域。

8. 发明申请

US20070075736A1 FPGA powerup to known functional state 失效
公开(公告)号：US20070075736A1
公开(公告)日：2007-04-05
申请号：US11371833
申请日：2006-03-09
申请人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
发明人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
IPC分类号： H03K19/177
CPC分类号： H03K19/177
摘要： A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

9. 发明申请

US20050278551A1 METHOD FOR SYSTEM LEVEL PROTECTION OF FIELD PROGRAMMABLE LOGIC DEVICES 失效
标题翻译：用于系统级保护现场可编程逻辑器件的方法
公开(公告)号：US20050278551A1
公开(公告)日：2005-12-15
申请号：US10709809
申请日：2004-05-28
申请人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds
发明人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds
IPC分类号： G06F21/00 , H04L9/32
CPC分类号： G06F21/76
摘要： A method for protecting a dynamically reconfigurable computing system includes generating an encoding signature and passing the encoding signature, through a system level bus, to at least one field programmable logic device and to a function library included within the system. The function library contains a plurality of functions for selective programming into the at least one field programmable logic device. A lock is generated so as to prevent external resources with respect to the system from accessing the encoding signature during the passing thereof.
摘要翻译：一种用于保护动态可重新配置的计算系统的方法包括生成编码签名并将编码签名通过系统级总线传递到至少一个现场可编程逻辑设备和包括在该系统内的功能库。功能库包含用于对至少一个现场可编程逻辑器件进行选择性编程的多个功能。生成锁，以防止相对于系统的外部资源在通过期间访问编码签名。

10. 发明申请

US20050121698A1 FPGA blocks with adjustable porosity pass thru 失效
标题翻译：具有可调节孔隙度的FPGA块通过
公开(公告)号：US20050121698A1
公开(公告)日：2005-06-09
申请号：US10731296
申请日：2003-12-09
申请人： Christopher Reynolds , Sebastian Ventrone , Angela Weil
发明人： Christopher Reynolds , Sebastian Ventrone , Angela Weil
IPC分类号： H01L27/10 , H01L27/118 , H03K19/177
CPC分类号： G06F17/5068 , H01L27/11803
摘要： A field programmable gate array is described for use in a semiconductor chip such as a VLSI chip. The array is provided with variable wire-through porosity to allow for optimum chip-level routing through the array. This is achieved by dividing the array into blocks which can be individually assessed for required porosity. Then blocks that have been prefabricated with differing porosities are placed in the macro to optimize local chip level routing. The routing of wires is determined by developing a chip floor plan to include early timing allocation and a proposed placement of the array. The floor plan is then overlaid with critical logical wiring nets. From this, an initial selection of blocks is made based on proposed wiring density, and the macro is assembled with the blocks strategically placed therein. The procedure is likewise applicable to other types of densely obstructed cores embedded with a chip.
摘要翻译：描述了用于诸如VLSI芯片的半导体芯片中的现场可编程门阵列。该阵列具有可变的线穿孔孔，以允许通过阵列的最佳芯片级布线。这是通过将阵列划分成可以单独评估所需孔隙度的块来实现的。然后将具有不同孔隙度的预制块放置在宏中以优化本地芯片级布线。通过开发芯片平面图来确定导线的布线，以包括早期的时序分配和阵列的建议放置。然后将平面图重叠在关键的逻辑布线网上。由此，基于所提出的布线密度进行块的初始选择，并且宏与被策略地放置在其中的块组装。该程序同样适用于嵌入芯片的其他类型的密封阻塞芯。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式