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    • 6. 发明授权
    • Test apparatus and manufacturing method
    • 试验装置及制造方法
    • US08892381B2
    • 2014-11-18
    • US13044320
    • 2011-03-09
    • Daisuke WatanabeToshiyuki Okayasu
    • Daisuke WatanabeToshiyuki Okayasu
    • G01R31/26G06F19/00G01R31/319G01R31/3185
    • G01R31/318511G01R31/31926
    • A test apparatus that tests a plurality of devices under test formed on a wafer under test includes a test substrate that faces the wafer under test and is electrically connected to the devices under test, a programmable device that is provided on the test substrate and changes a logic relationship of output logic data with respect to input logic data, according to program data supplied thereto, a plurality of input/output circuits that are provided on the test substrate to correspond to the devices under test and that each supply the corresponding device under test with a test signal corresponding to the output logic data of the programmable device, and a judging section that judges pass/fail of each device under test, based on operation results of each device under test according to the test signal.
    • 测试在被测晶片上形成的多个待测器件的测试装置包括面向被测晶片并与被测器件电连接的测试基板,设置在测试基板上的可编程器件, 输出逻辑数据相对于输入逻辑数据的逻辑关系,根据提供给其的程序数据,多个输入/输出电路,设置在测试基板上以对应于被测器件,并且每个输入/输出电路提供相应的被测器件 具有与可编程装置的输出逻辑数据相对应的测试信号,以及判定部,根据测试信号,根据被测设备的运算结果,判定各被测设备的通过/失败。
    • 8. 发明申请
    • INFORMATION PROCESSING APPARATUS AND METHOD
    • 信息处理装置和方法
    • US20130271577A1
    • 2013-10-17
    • US13976200
    • 2011-12-22
    • Daisuke WatanabeShinji UchiyamaDaisuke Kotake
    • Daisuke WatanabeShinji UchiyamaDaisuke Kotake
    • H04N13/02
    • H04N13/275G06T7/75G06T2207/10004G06T2207/10028
    • An information processing apparatus includes a model storing unit configured to store a three-dimensional form model for acquiring the position and posture of a measurement target object, an image acquiring unit configured to acquire an image of the measurement target object, a first position and posture acquiring unit configured to acquire a first position and posture of the three-dimensional form model in a first coordinate system on the basis of a first geometric feature of the three-dimensional form model and a first geometric feature within the image, and a second position and posture acquiring unit configured to acquire a second position and posture of the three-dimensional form model in a second coordinate system that is different from the first coordinate system on the basis of a second geometric feature of the three-dimensional form model and a second geometric feature within the image and the first position and posture.
    • 一种信息处理设备,包括:模型存储单元,被配置为存储用于获取测量目标对象的位置和姿势的三维形式模型;图像获取单元,被配置为获取测量目标对象的图像,第一位置和姿势 获取单元,被配置为基于所述三维形式模型的第一几何特征和所述图像内的第一几何特征获取第一坐标系中的所述三维形式模型的第一位置和姿势,以及第二位置 以及姿势获取单元,被配置为基于所述三维形式模型的第二几何特征,在与所述第一坐标系不同的第二坐标系中获取所述三维形式模型的第二位置和姿势;以及第二 图像内的几何特征和第一位置和姿势。
    • 9. 发明授权
    • Clock data recovery circuit and method
    • 时钟数据恢复电路及方法
    • US08537935B2
    • 2013-09-17
    • US12532132
    • 2008-03-18
    • Daisuke WatanabeToshiyuki Okayasu
    • Daisuke WatanabeToshiyuki Okayasu
    • H03D3/18H03D3/24
    • H04L7/033G01R31/31727G01R31/31937H03L7/0812H04L7/0037
    • A change-point detection circuit 16 extracts a clock signal from serial data, input data. A variable delay circuit provides a delay in accordance with a delay control signal to a reference signal having a predetermined frequency, so that the phase of the reference signal is shifted on the basis of an initial delay. An input latch circuit latches internal serial data by using an output signal of the variable delay circuit as a strobe signal. A phase comparator matches the frequencies of the clock signal and the strobe signal with each other, and generates phase difference data in accordance with a phase difference between the two signals. A loop filter integrates the phase difference data generated by the phase comparator and outputs it as the delay control signal. The phase shift amount acquisition unit acquires a phase shift amount based on the delay control signal, the phase shift amount being based on the initial delay provided to the reference signal by the variable delay circuit.
    • 变化点检测电路16从串行数据,输入数据中提取时钟信号。 可变延迟电路根据具有预定频率的参考信号的延迟控制信号提供延迟,使得参考信号的相位基于初始延迟而偏移。 输入锁存电路通过使用可变延迟电路的输出信号作为选通信号来锁存内部串行数据。 相位比较器将时钟信号和选通信号的频率相互匹配,并根据两个信号之间的相位差产生相位差数据。 环路滤波器对相位比较器产生的相位差数据进行积分,并将其作为延迟控制信号输出。 相移量获取单元基于延迟控制信号获取相移量,相移量基于由可变延迟电路提供给参考信号的初始延迟。
    • 10. 发明授权
    • Test system and substrate unit for testing
    • 测试系统和基板单元进行测试
    • US08466702B2
    • 2013-06-18
    • US12953352
    • 2010-11-23
    • Daisuke WatanabeToshiyuki Okayasu
    • Daisuke WatanabeToshiyuki Okayasu
    • G01R31/20G01R31/02
    • G01R31/2889
    • A test system that tests a plurality of chips under test formed on a wafer under test, the test system comprising a plurality of test substrates that are arranged in overlapping layers and that each have a plurality of test circuits, whose function is determined for each wafer, formed thereon; a plurality of connecting sections that electrically connect, to the chips under test, the test circuits formed on one of the test substrates; and a control apparatus that controls each of the test circuits. Each test substrate has test circuits, with a function predetermined for each substrate, formed thereon.
    • 一种在被测晶片上测试被测试的多个待测芯片的测试系统,所述测试系统包括多个测试基板,所述多个测试基板布置在重叠层中,并且每个具有多个测试电路,每个测试电路的功能是针对每个晶片 ,形成在其上 多个连接部,其将与测试用芯片电连接的测试电路形成在一个测试基板上; 以及控制每个测试电路的控制装置。 每个测试基板具有在其上形成的具有对于每个基板预定的功能的测试电路。