专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08086975B2 Power aware asynchronous circuits 失效
标题翻译：功率感知异步电路
公开(公告)号：US08086975B2
公开(公告)日：2011-12-27
申请号：US12421963
申请日：2009-04-10
申请人： Ken Shiring , Peter A. Beerel , Andrew Lines , Arash Saifhashemi
发明人： Ken Shiring , Peter A. Beerel , Andrew Lines , Arash Saifhashemi
IPC分类号： G06F17/50
CPC分类号： G06F17/5059
摘要： Techniques are described for converting netlists for synchronous circuits such as combinational modules, flip flops (or latches), and clock gating modules, to netlist of asynchronous modules. Processes including algorithms are described that bundle multiple modules in an enable domain, so that they are activated only if the incoming enable token to the enable domain has the UPDATE value. The modules can be clustered inside an enable domain, so that each cluster has a separate controller. The objective function of bundling and clustering can minimize power consumption with respect to a given cycle time. Exemplary embodiments can include a gated multilevel domino template.
摘要翻译：描述了用于将诸如组合模块，触发器（或锁存器）和时钟门控模块的同步电路的网表转换为异步模块的网表的技术。描述包括算法的过程，其中包括启用域中的多个模块，以便仅当启用域的传入启用令牌具有UPDATE值时才激活它们。这些模块可以集群到启用域内，以便每个集群都有一个单独的控制器。捆绑和聚类的目标功能可以使给定周期时间的功耗最小化。示例性实施例可以包括门控多级多米诺骨牌模板。

2. 发明申请

US20090288058A1 POWER AWARE ASYNCHRONOUS CIRCUITS 失效
标题翻译：电源异常电路
公开(公告)号：US20090288058A1
公开(公告)日：2009-11-19
申请号：US12421963
申请日：2009-04-10
申请人： Ken Shiring , Peter A. Beerel , Andrew Lines , Arash Saifhashemi
发明人： Ken Shiring , Peter A. Beerel , Andrew Lines , Arash Saifhashemi
IPC分类号： G06F17/50
CPC分类号： G06F17/5059
摘要： Techniques are described for converting netlists for synchronous circuits such as combinational modules, flip flops (or latches), and clock gating modules, to netlist of asynchronous modules. Processes including algorithms are described that bundle multiple modules in an enable domain, so that they are activated only if the incoming enable token to the enable domain has the UPDATE value. The modules can be clustered inside an enable domain, so that each cluster has a separate controller. The objective function of bundling and clustering can minimize power consumption with respect to a given cycle time. Exemplary embodiments can include a gated multilevel domino template.
摘要翻译：描述了用于将诸如组合模块，触发器（或锁存器）和时钟门控模块的同步电路的网表转换为异步模块的网表的技术。描述包括算法的过程，其中包括启用域中的多个模块，以便仅当启用域的传入启用令牌具有UPDATE值时才激活它们。这些模块可以集群到启用域内，以便每个集群都有一个单独的控制器。捆绑和聚类的目标功能可以使给定周期时间的功耗最小化。示例性实施例可以包括门控多级多米诺骨牌模板。

3. 发明授权

US08448105B2 Clustering and fanout optimizations of asynchronous circuits 有权
标题翻译：异步电路的聚类和扇出优化
公开(公告)号：US08448105B2
公开(公告)日：2013-05-21
申请号：US12429772
申请日：2009-04-24
申请人： Georgios Dimou , Peter A. Beerel , Andrew Lines
发明人： Georgios Dimou , Peter A. Beerel , Andrew Lines
IPC分类号： G06F17/50
CPC分类号： G06F9/3869 , G06F17/5059
摘要： Techniques are described for generating asynchronous circuits from any arbitrary HDL representation of a synchronous circuit by automatically clustering the synthesized gates into pipeline stages that are then slack-matched to meet performance goals while minimizing area. Automatic pipelining can be provided in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The techniques are applicable to many asynchronous design styles. A model and infrastructure can be designed that guides clustering to avoid the introduction of deadlocks and achieve a target circuit performance. Slack matching models can be used to take advantage of fanout optimizations of buffer trees that improve the quality of the results.
摘要翻译：描述了用于通过将合成门自动聚集到流水线阶段中以从同步电路的任何任意HDL表示生成异步电路的技术，该流水线阶段随机松弛匹配以满足性能目标同时最小化面积。可以提供自动流水线，其中总体设计的吞吐量不限于原始RTL规范中的时钟频率或流水线级别。这些技术适用于许多异步设计风格。可以设计一个模型和基础设施，指导群集，以避免引入死锁并实现目标电路性能。松弛匹配模型可用于利用提升结果质量的缓冲树的优化。

4. 发明申请

US20090288059A1 CLUSTERING AND FANOUT OPTIMIZATIONS OF ASYNCHRONOUS CIRCUITS 有权
标题翻译：非线性电路的聚类和扇区优化
公开(公告)号：US20090288059A1
公开(公告)日：2009-11-19
申请号：US12429772
申请日：2009-04-24
申请人： Georgios Dimou , Peter A. Beerel , Andrew Lines
发明人： Georgios Dimou , Peter A. Beerel , Andrew Lines
IPC分类号： G06F17/50
CPC分类号： G06F9/3869 , G06F17/5059
摘要： Techniques are described for generating asynchronous circuits from any arbitrary HDL representation of a synchronous circuit by automatically clustering the synthesized gates into pipeline stages that are then slack-matched to meet performance goals while minimizing area. Automatic pipelining can be provided in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The techniques are applicable to many asynchronous design styles. A model and infrastructure can be designed that guides clustering to avoid the introduction of deadlocks and achieve a target circuit performance. Slack matching models can be used to take advantage of fanout optimizations of buffer trees that improve the quality of the results.
摘要翻译：描述了用于通过将合成门自动聚集到流水线阶段中以从同步电路的任何任意HDL表示生成异步电路的技术，该流水线阶段松弛匹配以满足性能目标同时最小化面积。可以提供自动流水线，其中总体设计的吞吐量不限于原始RTL规范中的时钟频率或流水线级别。这些技术适用于许多异步设计风格。可以设计一个模型和基础设施，指导群集，以避免引入死锁并实现目标电路性能。松弛匹配模型可用于利用提升结果质量的缓冲树的优化。

5. 发明授权

US08495543B2 Multi-level domino, bundled data, and mixed templates 有权
标题翻译：多级多米诺骨牌，捆绑数据和混合模板
公开(公告)号：US08495543B2
公开(公告)日：2013-07-23
申请号：US12527187
申请日：2009-06-17
申请人： Georgios Dimou , Peter A. Beerel , Andrew Lines
发明人： Georgios Dimou , Peter A. Beerel , Andrew Lines
IPC分类号： G06F17/50
CPC分类号： H03K19/096 , G06F17/505
摘要： Techniques are described for generating asynchronous circuits (e.g., in the form of one or more netlists) for implementation, e.g., in integrated circuitry/chips. Embodiments are directed to asynchronous multi-level domino design template and several variants including a mixture of domino and single-rail data logic. The templates can provide high throughput, low latency, and area efficiency. A multi-level domino template is partitioned into pipeline stages in which each stage consists of potentially multiple-levels of domino logic controlled by a single controller that communicates with other controllers via handshaking. Each stage is composed of two parts: a data path and a control path. The data path implements the computational logic, both combinational and sequential using efficient dual-rail domino logic. The control path implements a unique four-phase handshake to ensure correctness and the preservation of logical dependencies between pipeline stages. The data path and controller interact through a small number of key control signals.
摘要翻译：描述了用于生成用于实现的异步电路（例如，以一个或多个网表的形式）的技术，例如在集成电路/芯片中。实施例涉及异步多级多米诺骨牌设计模板和几种变型，包括多米诺骨牌和单轨数据逻辑的混合。模板可以提供高吞吐量，低延迟和面积效率。多层次的多米诺骨牌模板被划分为流水线阶段，其中每个阶段由潜在的多层次的多米诺骨牌组成，由单个控制器控制，通过握手与其他控制器进行通信。每个阶段由两部分组成：数据路径和控制路径。数据路径实现计算逻辑，组合和顺序使用有效的双轨多米诺骨牌逻辑。控制路径实现了唯一的四相握手，以确保流水线阶段之间的正确性和逻辑依赖性的保持。数据路径和控制器通过少量关键控制信号进行交互。

6. 发明申请

US20110029941A1 MULTI-LEVEL DOMINO, BUNDLED DATA, AND MIXED TEMPLATES 有权
标题翻译：多层面多米诺，填充数据和混合模板
公开(公告)号：US20110029941A1
公开(公告)日：2011-02-03
申请号：US12527187
申请日：2009-06-17
申请人： Georgios Dimou , Peter A. Beerel , Andrew Lines
发明人： Georgios Dimou , Peter A. Beerel , Andrew Lines
IPC分类号： G06F17/50
CPC分类号： H03K19/096 , G06F17/505
摘要： Techniques are described for generating asynchronous circuits (e.g., in the form of one or more netlists) for implementation, e.g., in integrated circuitry/chips. Embodiments are directed to asynchronous multi-level domino design template and several variants including a mixture of domino and single-rail data logic. The templates can provide high throughput, low latency, and area efficiency. A multi-level domino template is partitioned into pipeline stages in which each stage consists of potentially multiple-levels of domino logic controlled by a single controller that communicates with other controllers via handshaking. Each stage is composed of two parts: a data path and a control path. The data path implements the computational logic, both combinational and sequential using efficient dual-rail domino logic. The control path implements a unique four-phase handshake to ensure correctness and the preservation of logical dependencies between pipeline stages. The data path and controller interact through a small number of key control signals.
摘要翻译：描述了用于生成用于实现的异步电路（例如，以一个或多个网表的形式）的技术，例如在集成电路/芯片中。实施例涉及异步多级多米诺骨牌设计模板和几种变型，包括多米诺骨牌和单轨数据逻辑的混合。模板可以提供高吞吐量，低延迟和面积效率。多层次的多米诺骨牌模板被划分为流水线阶段，其中每个阶段由潜在的多层次的多米诺骨牌组成，由单个控制器控制，通过握手与其他控制器进行通信。每个阶段由两部分组成：数据路径和控制路径。数据路径实现计算逻辑，组合和顺序使用有效的双轨多米诺骨牌逻辑。控制路径实现了唯一的四相握手，以确保流水线阶段之间的正确性和逻辑依赖性的保持。数据路径和控制器通过少量关键控制信号进行交互。

7. 发明授权

US09558309B2 Timing violation resilient asynchronous template 有权
标题翻译：定时违规弹性异步模板
公开(公告)号：US09558309B2
公开(公告)日：2017-01-31
申请号：US14702426
申请日：2015-05-01
申请人： Peter A. Beerel , Melvin Breuer , Benmao Cheng , Dylan Hand
发明人： Peter A. Beerel , Melvin Breuer , Benmao Cheng , Dylan Hand
IPC分类号： H03K19/00 , G06F17/50 , H03K3/037 , H03K19/003 , H03K19/096
CPC分类号： G06F17/505 , G06F17/5031 , G06F17/5059 , G06F2217/62 , G06F2217/84 , H03K3/037 , H03K3/0375 , H03K19/003 , H03K19/00323 , H03K19/0966
摘要： An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.
摘要翻译：异步电路可以包括单轨逻辑数据通路; 一个或多个错误检测锁存器; 控制器，用于控制错误检测锁存器; 和延迟线。在错误检测锁存器指示是否发生错误之前，控制器和延迟线可以协作以与一个或多个其他控制器进行通信，即受控错误检测锁存器的输出可能是有效的。

8. 发明授权

US5941982A Efficient self-timed marking of lengthy variable length instructions 失效
标题翻译：长时间可变长度指令的高效自定时标记
公开(公告)号：US5941982A
公开(公告)日：1999-08-24
申请号：US997461
申请日：1997-12-23
申请人： Ran Ginosar , Rakefet Kol , Kenneth Scott Stevens , Peter A. Beerel , Kenneth Yi Yun , Christopher John Myers , Shai Rotem
发明人： Ran Ginosar , Rakefet Kol , Kenneth Scott Stevens , Peter A. Beerel , Kenneth Yi Yun , Christopher John Myers , Shai Rotem
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816
摘要： A self-timed instruction marking circuit includes a long instruction processing system to divide long instruction processing between two columns of the instruction marking circuit. Length decoders are interconnected across columns to signal the presence and length of long instructions. Self-timed marking can continue without alteration. The number of connections required by the instruction marking circuit are reduced. The marking process can be optimized to efficiently process all instructions by setting the definition of a long instruction such that commonly executed instructions are not included.
摘要翻译：自定时指令标记电路包括用于在指令标记电路的两列之间分割长指令处理的长指令处理系统。长度解码器通过列互连，以指示长指令的存在和长度。自动打标可以继续而不改变。指令标记电路所需的连接数量减少。可以优化标记过程以通过设置长指令的定义来有效地处理所有指令，使得不包括通常执行的指令。

9. 发明授权

US07197691B2 Reduced-latency soft-in/soft-out module 有权
标题翻译：降低延迟软启/退出模块
公开(公告)号：US07197691B2
公开(公告)日：2007-03-27
申请号：US10875979
申请日：2004-06-24
申请人： Peter A. Beerel , Keith M. Chugg , Georgios D. Dimou , Phunsak Thiennviboon
发明人： Peter A. Beerel , Keith M. Chugg , Georgios D. Dimou , Phunsak Thiennviboon
IPC分类号： H03M13/03
CPC分类号： H03M13/3905 , H03M13/2957 , H03M13/3966 , H03M13/6572
摘要： Decoding an encoded signal (for example, a turbo encoded signal, a block encoded signal or the like) is performed by demodulating the received encoded signal to produce soft information, and iteratively processing the soft information with one or more soft-in/soft-output (SISO) modules. At least one of the SISO modules uses a tree structure to compute forward and backward state metrics. More generally, iterative detection is performed by receiving an input signal corresponding to one or more outputs of a module whose soft-inverse can be computed by running the forward-backward algorithm on a trellis representation of the module, and determining the soft inverse of the module by computing forward and backward state metrics of the received input signal using a tree structure.
摘要翻译：通过解调接收到的编码信号以产生软信息来对编码信号（例如，turbo编码信号，块编码信号等）进行解码，并且利用一个或多个软/软编码信号迭代地处理软信息，输出（SISO）模块。至少有一个SISO模块使用树结构来计算前向和后向状态度量。更一般地，通过接收与模块的一个或多个输出相对应的输入信号来执行迭代检测，该模块的软反转可以通过在模块的网格表示上运行前向后向算法来计算，并且确定模块，通过使用树结构计算所接收的输入信号的前向和后向状态度量。

10. 发明授权

US06526551B2 Formal verification of a logic design through implicit enumeration of strongly connected components 失效
公开(公告)号：US06526551B2
公开(公告)日：2003-02-25
申请号：US09894769
申请日：2001-06-28
申请人： Aiguo Xie , Peter A. Beerel
发明人： Aiguo Xie , Peter A. Beerel
IPC分类号： G06F945
CPC分类号： G06F17/504
摘要： Formal verification of a logic design through implicit enumeration of strongly connected components. The invention provides for efficient, cost-effective formal verification of logical circuits and systems using a method that is much less computationally expensive than other known methods. A digraph is recursively decomposed using reachability analysis. Non-trivial, strongly connected components derived through the use of the invention can be compared to expected behavior of a circuit or system. Alternatively, the invention can be applied to detect so-called “bad cycles” which are encountered in many formal verification problems.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式