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    • 4. 发明授权
    • Data management in flash memory using probability of charge disturbances
    • 使用电荷扰动概率的闪存中的数据管理
    • US08649215B2
    • 2014-02-11
    • US12930017
    • 2010-12-22
    • Luiz M. Franca-NetoRichard Leo GalbraithTravis Roger Oenning
    • Luiz M. Franca-NetoRichard Leo GalbraithTravis Roger Oenning
    • G11C16/34G11C16/06G11C29/00G11C29/44
    • G11C16/3495G11C29/50G11C2029/5002
    • A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix can also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which charge-disturb errors are provoked by executing a selected operation until a detectable error occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population.
    • 描述了使用系统对充电干扰操作的灵敏度和系统执行的充电干扰操作的历史的数据管理的闪存系统和方法。 在本发明的一个实施例中,对电荷干扰操作的灵敏度体现在干扰强度矩阵中,其中所选择的操作具有相关联的数值,该相关数值是该操作的相对强度的估计,以引起电荷干扰,导致导致 数据错误。 干扰强度矩阵还可以包括指示电荷增益或损失的误差方向。 扰动强度矩阵可以由进行自检的装置确定,其中通过执行所选择的操作而引起充电扰乱错误,直到出现可检测的错误。 在替代实施例中,通过从均匀群体测试所选择的单位来确定干扰强度矩阵。
    • 5. 发明授权
    • Data management in flash memory using probability of charge disturbances
    • 使用电荷扰动概率的闪存中的数据管理
    • US08599609B2
    • 2013-12-03
    • US12930013
    • 2010-12-22
    • Luiz M. Franca-NetoRichard Leo GalbraithTravis Roger Oenning
    • Luiz M. Franca-NetoRichard Leo GalbraithTravis Roger Oenning
    • G11C11/04G11C16/04
    • G11C29/50G06F11/1048G11C2029/5002
    • A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix should also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which changes in the measured dispersion value are provoked by executing a selected operation until a detectable change occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population.
    • 描述了使用系统对充电干扰操作的灵敏度和系统执行的充电干扰操作的历史的数据管理的闪存系统和方法。 在本发明的一个实施例中,对电荷干扰操作的灵敏度体现在干扰强度矩阵中,其中所选择的操作具有相关联的数值,该相关联的数值是该操作的相对强度的估计,导致电荷干扰导致 数据错误。 干扰强度矩阵还应包括指示电荷增益或损失的误差方向。 干扰强度矩阵可以由进行自检的装置确定,其中通过执行所选择的操作来激发测量的色散值的变化,直到发生可检测的变化。 在替代实施例中,通过从均匀群体测试所选择的单位来确定干扰强度矩阵。
    • 6. 发明授权
    • Early degradation detection in flash memory using test cells
    • 使用测试单元的闪存中的早期劣化检测
    • US08422303B2
    • 2013-04-16
    • US12930020
    • 2010-12-22
    • Luiz M. Franca-NetoRichard Leo GalbraithTravis Roger Oenning
    • Luiz M. Franca-NetoRichard Leo GalbraithTravis Roger Oenning
    • G11C11/34
    • G11C11/5642G11C16/00G11C16/3418G11C16/349G11C29/24G11C29/50004G11C2211/5634
    • A Flash memory system and a method for data management using the embodiments of the invention use special test cells with Early Degradation Detection (EDD) circuitry instead of using the actual user-data storage cells are described. The Flash memory test cells can be made to serve as a “canary in a coal mine” by being made more sensitive than the standard cells by using experimentally determined sensitive write VT and variable read VT. Techniques for early degradation detection (EDD) in Flash memories measure the dispersion of the threshold voltages (VT's), of a set (e.g. page) of NAND Flash memory cells during read operations. In an embodiment of the invention the time-to-completion (TTC) values for the read operation for the memory cells are used as a proxy for dispersion of the threshold voltages (VT's). A Dispersion Analyzer determines the dispersion of the set of TTC values.
    • 描述使用本发明的实施例的闪存系统和数据管理方法,使用具有早期降解检测(EDD)电路的特殊测试单元而不是使用实际的用户数据存储单元。 通过使用实验确定的敏感写入VT和可变读取VT,闪存测试单元可以通过使其比标准单元更敏感,作为煤矿中的金丝雀。 用于闪速存储器中的早期劣化检测(EDD)的技术测量读取操作期间的一组(例如,页)NAND闪存单元的阈值电压(VT)的偏差。 在本发明的一个实施例中,用于存储器单元的读取操作的完成时间(TTC)值用作阈值电压(VT)的色散的代理。 色散分析仪确定一组TTC值的色散。
    • 9. 发明授权
    • Method and apparatus for performing DC offset cancellation in a receiver
    • 用于在接收机中执行DC偏移消除的方法和装置
    • US07233780B2
    • 2007-06-19
    • US10785783
    • 2004-02-24
    • Luiz M. Franca-Neto
    • Luiz M. Franca-Neto
    • H04B1/10
    • H03F3/45982H03F2200/294H03F2200/372H04B1/30
    • An amplification system for reducing DC offset in an input signal uses a low pass filter to isolate a DC component of the input signal. The system then subtracts the DC component from the input signal. In one embodiment, the system includes first and second amplifiers in addition to the low pass filter. The first amplifier amplifies the input signal to generate a first amplified signal at a differential output port of the amplification system. The second amplifier amplifies a low pass filtered version of the input signal to generate a second amplified signal at the differential output port of the amplification system. The outputs of the first and second amplifiers are connected to the differential output port of the amplification system in such a way that the first and second signals combine 180 degrees out of phase at the output port. An automatic gain control circuit is also provided that automatically adjusts the gain of the amplification system without changing a bias level associated with the first and second amplifiers.
    • 用于减少输入信号中的DC偏移的放大系统使用低通滤波器来隔离输入信号的DC分量。 然后系统从输入信号中减去直流分量。 在一个实施例中,该系统除了低通滤波器之外还包括第一和第二放大器。 第一放大器放大输入信号以在放大系统的差分输出端口处产生第一放大信号。 第二放大器放大输入信号的低通滤波版本,以在放大系统的差分输出端口产生第二放大信号。 第一和第二放大器的输出端连接到放大系统的差分输出端口,使得第一和第二信号在输出端口处组合180度异相。 还提供一种自动增益控制电路,其自动调节放大系统的增益,而不改变与第一和第二放大器相关联的偏置电平。
    • 10. 发明授权
    • Ultra wide band low noise amplifier and method
    • 超宽带低噪声放大器及方法
    • US06806777B2
    • 2004-10-19
    • US10336341
    • 2003-01-02
    • Luiz M. Franca-Neto
    • Luiz M. Franca-Neto
    • H03F304
    • H03F3/211H03F3/193H03F2200/294H03F2200/372H03F2200/72
    • An ultra wide band (UWB) low noise amplifier (LNA) includes a common-gate (CG) amplifying element in cascode with a common-source (CS) amplifying element, and a load-tracking (LT) network to, at least in part, track a changing output impedance of the cascode helping to provide a substantially constant gain over an ultra wide frequency band of interest. The LT network may include of a parallel combination of a capacitive element, an inductive element, and a resistive element, which may be selected to, at least in part, track the changing output impedance of the cascode over an ultra wide frequency band. An initial common-gate stage may compensate for a capacitive input impedance of the cascode and may provide a substantially matched antenna input over the ultra wide frequency band. The amplifier may also include one or more resistor-based amplifying stages after the cascode.
    • 超宽带(UWB)低噪声放大器(LNA)包括与共源(CS)放大元件和负载跟踪(LT)网络共源共栅的共栅(CG)放大元件,至少在 跟踪变化的共源共栅的输出阻抗,有助于在感兴趣的超宽频带上提供基本恒定的增益。 LT网络可以包括电容元件,电感元件和电阻元件的并联组合,其可以被选择为至少部分地在超宽频带上跟踪共源共栅的变化的输出阻抗。 初始共栅极级可以补偿共源共栅的电容性输入阻抗,并且可以在超宽频带上提供基本匹配的天线输入。 放大器还可以包括在共源共栅之后的一个或多个基于电阻的放大级。