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1. 发明授权

US6025794A Signal transmission circuit, signal transmission method A/D converter and solid-state imaging element 失效
标题翻译：信号传输电路，信号传输方式A / D转换器和固态成像元件
公开(公告)号：US6025794A
公开(公告)日：2000-02-15
申请号：US792769
申请日：1997-02-03
申请人： Keiichi Kusumoto , Akira Matsuzawa , Kenji Murata , Youichi Okamoto
发明人： Keiichi Kusumoto , Akira Matsuzawa , Kenji Murata , Youichi Okamoto
IPC分类号： H03M1/12 , H03M1/14 , H03M1/36
CPC分类号： H03M1/1245 , H03M1/146 , H03M1/204 , H03M1/365
摘要： According to the present invention, a signal transmission circuit for receiving an input signal and outputting an output signal corresponding to the input signal is provided. The signal transmission circuit includes: a first capacitance; an electric charge supply section for supplying electric charge corresponding to the input signal to the first capacitance; a second capacitance; and a transfer section for transferring the electric charge from the first capacitance to the second capacitance. In the signal transmission circuit, the second capacitance is larger than the first capacitance.
摘要翻译：根据本发明，提供一种用于接收输入信号并输出与输入信号对应的输出信号的信号传输电路。信号传输电路包括：第一电容; 电荷供给部，用于将对应于所述输入信号的电荷提供给所述第一电容; 第二电容; 以及用于将电荷从第一电容转移到第二电容的转移部分。在信号传输电路中，第二电容大于第一电容。

2. 发明授权

US5717624A Analog memory circuit and method for recording analog signal 失效
标题翻译：模拟记忆电路和记录模拟信号的方法
公开(公告)号：US5717624A
公开(公告)日：1998-02-10
申请号：US739867
申请日：1996-10-31
申请人： Keiichi Kusumoto , Kenji Murata , Yutaka Terada , Akira Matsuzawa
发明人： Keiichi Kusumoto , Kenji Murata , Yutaka Terada , Akira Matsuzawa
IPC分类号： G11C27/02 , G11C27/00
CPC分类号： G11C27/026
摘要： An analog memory circuit of the present invention includes: a recording circuit for recording and holding an input analog signal as a charge and for reading out the analog signal after deterioration of the analog signal caused by leakage of the charge in a holding operation is eliminated; a selecting circuit for controlling an operation of the recording circuit; and a driving circuit for supplying a predetermined constant voltage to the recording circuit, wherein the recording circuit includes: an input/output terminal for inputting and outputting the analog signal; a first capacitor having a first electrode and a second electrode, for recording and holding the analog signal as the charge; and a second capacitor connected between the second electrode of the first capacitor and a reference potential, for holding a charge leaked from the first capacitor, and wherein an amount of charge corresponding to an amount of leaked charge held in the second capacitor is restored to the first capacitor with predetermined timing.
摘要翻译：本发明的模拟存储器电路包括：记录电路，用于记录和保持作为电荷的输入模拟信号，并且用于在由保持操作中的电荷泄漏引起的模拟信号劣化后读出模拟信号; 用于控制记录电路的操作的选择电路; 以及用于向所述记录电路提供预定的恒定电压的驱动电路，其中所述记录电路包括：用于输入和输出所述模拟信号的输入/输出端子; 具有第一电极和第二电极的第一电容器，用于记录和保持模拟信号作为电荷; 以及连接在第一电容器的第二电极和参考电位之间的第二电容器，用于保持从第一电容器泄漏的电荷，并且其中对应于保持在第二电容器中的泄漏电荷量的电荷量恢复到具有预定定时的第一电容器。

3. 发明授权

US5719513A Latch circuit for amplifying an analog signal and converting an analog signal into a digital signal 失效
标题翻译：用于放大模拟信号并将模拟信号转换为数字信号的锁存电路
公开(公告)号：US5719513A
公开(公告)日：1998-02-17
申请号：US699808
申请日：1996-08-20
申请人： Keiichi Kusumoto , Kenji Murata , Akira Matsuzawa
发明人： Keiichi Kusumoto , Kenji Murata , Akira Matsuzawa
IPC分类号： H03K3/012 , H03K3/037
CPC分类号： H03K3/037 , H03K3/012
摘要： The present invention discloses an improved latch circuit. In the latch circuit, a composite gate takes in a basic clock signal and a delayed clock signal which is delayed by a delay circuit for a specific amount with respect to the basic clock signal, and puts out to a second drive circuit a first signal identical in waveform with the basic block signal, and further puts out to a first drive circuit a second signal that is delayed in the rising timing with respect to the first signal. As a result of such arrangement, when a transition is made from a feedback period during which an input switch has an off state while a feedback switch has an on state to a sampling period during which the input switch has an on state while the feedback switch has an off state, neither the input switch nor the feedback switch has an on state.
摘要翻译：本发明公开了一种改进的锁存电路。在锁存电路中，复合栅极接收基本时钟信号和相对于基本时钟信号延迟特定量的延迟电路的延迟时钟信号，并向第二驱动电路输出相同的第一信号具有基本块信号的波形，并且进一步向第一驱动电路输出相对于第一信号在上升定时中延迟的第二信号。作为这种布置的结果，当反馈开关具有断开状态的反馈周期转变到反馈开关具有接通状态到输入开关处于导通状态的采样周期，而反馈开关具有断开状态，输入开关和反馈开关都不具有导通状态。

4. 发明授权

US5828717A Time counting circuit and counter circuit 失效
标题翻译：计时电路和计数器电路
公开(公告)号：US5828717A
公开(公告)日：1998-10-27
申请号：US624960
申请日：1996-03-27
申请人： Keiichi Kusumoto , Shiro Dosho , Yutaka Terada , Akira Matsuzawa
发明人： Keiichi Kusumoto , Shiro Dosho , Yutaka Terada , Akira Matsuzawa
IPC分类号： G01R29/027 , G01C21/00
CPC分类号： G01R29/0273
摘要： There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption. An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition. A time-difference operating circuit corrects the numeric data outputted from the signal converting circuit based on the number of circulations of signal transition outputted from the counter circuit to provide time data, while calculating and outputting the pulse spacing of the pulse signal to be measured.
摘要翻译：提供了一种用于以高精度和低功耗测量脉冲信号的脉冲间隔的时间计数电路。由连接在环上的奇数个反相器组成的逆变器环振荡，并且一个信号转换发生在似乎在逆变器环周围似乎循环。连接到构成逆变器环的逆变器的各个输出端子的保持电路在待测脉冲信号的上升沿同时输出从逆变器输出的信号。然后，输出的信号由信号转换电路转换成数字数据。连接到构成逆变器环的逆变器之一的输出端的计数器电路对信号转换的循环数进行计数。时差操作电路根据从计数器电路输出的信号转换的循环数来校正从信号转换电路输出的数字数据，以提供时间数据，同时计算并输出要测量的脉冲信号的脉冲间隔。

5. 发明授权

US06201382B1 Low noise and energy loss power supply apparatus and voltage converter 失效
标题翻译：低噪声和能量损耗电源装置和电压转换器
公开(公告)号：US06201382B1
公开(公告)日：2001-03-13
申请号：US09284141
申请日：1999-06-11
申请人： Keiichi Kusumoto , Akira Matsuzawa
发明人： Keiichi Kusumoto , Akira Matsuzawa
IPC分类号： H01F2742
CPC分类号： H02M7/537 , H02M3/155 , H02M3/158
摘要： A power supply apparatus 200 comprises an energy supplying circuit 210 for supplying energy at a predetermined timing, and an energy preserving circuit 220 for receiving the energy supplied from the energy supplying circuit 210 and preserving the energy. The energy preserving circuit 220 includes an inductor 221, a capacitance 223 connected to one end of the inductor 221 at a node 222, and a capacitance 225 connected to the other end of the inductor 221 at a node 224. Energy is supplied to a load via at least one of the node 222 and the node 224.
摘要翻译：电源装置200包括用于在预定定时提供能量的能量供应电路210，以及用于接收从能量供应电路210提供的能量并保持能量的能量保存电路220。能量保存电路220包括电感器221，在节点222处连接到电感器221的一端的电容223和在节点224处连接到电感器221的另一端的电容225.能量被供应到负载经由节点222和节点224中的至少一个。

6. 发明授权

US5973523A Time counting circuit, sampling circuit, skew adjusting circuit, and logic analyzing circuit 失效
标题翻译：时间计数电路，采样电路，偏斜调整电路和逻辑分析电路
公开(公告)号：US5973523A
公开(公告)日：1999-10-26
申请号：US99456
申请日：1998-06-18
申请人： Keiichi Kusumoto , Akira Matsuzawa
发明人： Keiichi Kusumoto , Akira Matsuzawa
IPC分类号： G01R23/10 , G01R29/02 , G06F1/10 , G06F11/25 , H03K23/00 , H03K23/54 , H03M1/50 , H03M1/64 , H03L7/00
CPC分类号： G04F10/005 , G01R29/02 , G06F1/10 , G06F11/25
摘要： There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal. A row of holding circuits consists of a plurality of holding circuits connected to the output terminals of the respective sampling circuits and holds the output signals from the sampling circuits in response to a direction indicated by the second switch signal. An operating circuit calculates the pulse spacing of the pulse signal to be measured based on a logic level signal outputted from the row of holding circuits.
摘要翻译：提供了一种时间计数电路，其高精度地测量脉冲信号的脉冲间隔，并且对电源电压的变化表现出高的抵抗能力。延迟电路环由以环形配置连接的多个延迟电路组成，并且使信号转变通过振荡在延迟电路环周围循环。开关信号发生电路基于要测量的脉冲信号上升的时间输出第一和第二开关信号。一行采样电路由连接到各个延迟电路的输出端的多个采样电路组成，并响应于第一开关信号指示的方向对来自延迟电路的输出信号进行采样。一行保持电路由多个保持电路组成，多个保持电路连接到相应采样电路的输出端，并响应于第二开关信号指示的方向保持来自采样电路的输出信号。操作电路基于从保持电路行输出的逻辑电平信号来计算要测量的脉冲信号的脉冲间隔。

7. 发明授权

US5945935A A/D converter and A/D conversion method 失效
标题翻译： A / D转换器和A / D转换方法
公开(公告)号：US5945935A
公开(公告)日：1999-08-31
申请号：US974708
申请日：1997-11-19
申请人： Keiichi Kusumoto , Akira Matsuzawa
发明人： Keiichi Kusumoto , Akira Matsuzawa
IPC分类号： H03M1/36
CPC分类号： H03M1/206 , H03M1/365 , H03M1/50
摘要： The A/D converter realizes a high-rate and high-precision A/D conversion using amplifier circuits. Each amplifier circuit amplifies a difference between the voltage of an analog signal to be converted and a predetermined reference voltage. Each bank of holding circuits holds the output signals of an oscillator circuit, the levels of which signals are variable with the passage of time, when the output voltage of the associated amplifier circuit exceeds a predetermined value. The signals held in each said bank of holding circuits are output as a value representing the amplification time of the associated amplifier circuit. An operation means identifies a first amplifier circuit having a reference voltage higher than the analog signal voltage and a second amplifier circuit having a reference voltage lower than the analog signal voltage based on the values representing the amplification times, and determines a voltage, at a point interiorly dividing a difference between the reference voltages of the first and the second amplifier circuits by a ratio of the amplification time of the second amplifier circuit to the amplification time of the first amplifier circuit, as the analog signal voltage, thereby computing a digital value representing the analog signal.
摘要翻译： A / D转换器使用放大器电路实现高速率和高精度的A / D转换。每个放大器电路放大要转换的模拟信号的电压与预定参考电压之间的差。每个保持电路组保持振荡器电路的输出信号，当相关联的放大器电路的输出电压超过预定值时，其电平随着时间的推移而变化。保持在每个保持电路组中的信号作为表示相关放大器电路的放大时间的值被输出。操作装置识别具有高于模拟信号电压的参考电压的第一放大器电路和基于表示放大时间的值的具有低于模拟信号电压的参考电压的第二放大器电路，并且在一点上确定电压以第二放大电路的放大时间与第一放大电路的放大时间的比值将第一和第二放大器电路的参考电压之间的差分内部划分为模拟信号电压，由此计算代表模拟信号。

8. 发明授权

US5982841A Time counting circuit, pulse converting circuit and FM demodulating circuit 失效
标题翻译：时间计数电路，脉冲转换电路和FM解调电路
公开(公告)号：US5982841A
公开(公告)日：1999-11-09
申请号：US747180
申请日：1996-11-12
申请人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
发明人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
IPC分类号： G01R29/027 , H03D3/04 , H03K9/06 , H03M1/50 , G01M3/00
CPC分类号： G04F10/005 , G01R29/027 , H03D3/04 , H03K9/06
摘要： Provided is a time counting circuit which can measure the time taken from the rising edge to the falling edge of a pulse signal and the time from the falling edge to the rising edge thereof. The time counting circuit according to the present invention comprises a measuring circuit for measuring the time between either of the rising and falling edges of the pulse signal, and a pulse converting circuit for converting a pulse signal to be measured to a pulse signal having either of the edges in accordance with the rising edge of the pulse signal to be measured and having either of the edges in accordance with the falling edge of the pulse signal to be measured. The time between either of the edges of the pulse signal converted by the pulse converting circuit is measured by the measuring circuit. The time obtained by measurement is the time taken from the rising edge to the falling edge of the pulse signal to be measured or the time taken from the falling edge to the rising edge thereof.
摘要翻译：提供了一种时间计数电路，其可以测量从脉冲信号的上升沿到下降沿的时间以及从下降沿到上升沿的时间。根据本发明的计时电路包括：测量脉冲信号的上升沿和下降沿之间的时间的测量电路;以及脉冲转换电路，用于将要测量的脉冲信号转换成具有根据要测量的脉冲信号的上升沿的边缘，并根据要测量的脉冲信号的下降沿具有任一边缘。由脉冲转换电路转换的脉冲信号的任一边之间的时间由测量电路测量。通过测量获得的时间是从要测量的脉冲信号的上升沿到下降沿或从下降沿到其上升沿的时间所花费的时间。

9. 发明授权

US5920209A Time counting circuit, sampling circuit, skew adjusting circuit, and logic analyzing circuit 失效
公开(公告)号：US5920209A
公开(公告)日：1999-07-06
申请号：US99455
申请日：1998-06-18
申请人： Keiichi Kusumoto , Akira Matsuzawa
发明人： Keiichi Kusumoto , Akira Matsuzawa
IPC分类号： G01R23/10 , G01R29/02 , G06F1/10 , G06F11/25 , H03K23/00 , H03K23/54 , H03M1/50 , H03M1/64 , H03K19/0175
CPC分类号： G04F10/005 , G01R29/02 , G06F1/10 , G06F11/25
摘要： There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal. A row of holding circuits consists of a plurality of holding circuits connected to the output terminals of the respective sampling circuits and holds the output signals from the sampling circuits in response to a direction indicated by the second switch signal. An operating circuit calculates the pulse spacing of the pulse signal to be measured based on a logic level signal outputted from the row of holding circuits.

10. 发明授权

US5465093A Analog-to-digital converter 失效
标题翻译：模数转换器
公开(公告)号：US5465093A
公开(公告)日：1995-11-07
申请号：US128654
申请日：1993-09-30
申请人： Keiichi Kusumoto , Akira Matsuzawa
发明人： Keiichi Kusumoto , Akira Matsuzawa
IPC分类号： H03M1/10 , H03M1/06 , H03M1/14 , H03M1/20 , H03M1/34 , H03M1/36
CPC分类号： H03M1/204 , H03M1/0602 , H03M1/142 , H03M1/365
摘要： The present invention discloses an improved analog-to-digital converter. A second sampling circuit samples the voltage difference between an analog signal and a reference voltage, before a first sampling circuit moves to a follow operation from a sample operation. Owing to pipelining by the first and second sampling circuits, even after the first sampling circuit moves to a follow operation, the difference between an analog signal and a reference voltage is still applied to a logical-level amplifier. The output of the logical-level amplifier, amplified to a logical voltage, is converted by a logic device into an A/D conversion output. Therefore, ADC differential non linearity error can be reduced.
摘要翻译：本发明公开了一种改进的模数转换器。在第一采样电路从采样操作移动到跟随操作之前，第二采样电路对模拟信号和参考电压之间的电压差进行采样。由于第一和第二采样电路的流水线，即使在第一采样电路移动到跟随操作之后，模拟信号和参考电压之间的差仍然被施加到逻辑电平放大器。放大到逻辑电压的逻辑电平放大器的输出由逻辑器件转换为A / D转换输出。因此，可以减小ADC差分非线性误差。

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