专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5835552A Time counting circuit and counter circuit 失效
公开(公告)号：US5835552A
公开(公告)日：1998-11-10
申请号：US747129
申请日：1996-11-12
申请人： Keiichi Kusumoto , Shiro Dosho , Yutaka Terada , Akira Matsuzawa
发明人： Keiichi Kusumoto , Shiro Dosho , Yutaka Terada , Akira Matsuzawa
IPC分类号： G01R29/027 , H03D3/04 , H03K9/06 , H03M1/50 , G01B7/00
CPC分类号： G04F10/005 , G01R29/027 , H03D3/04 , H03K9/06
摘要： There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption. An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition. A time-difference operating circuit corrects the numeric data outputted from the signal converting circuit based on the number of circulations of signal transition outputted from the counter circuit to provide time data, while calculating and outputting the pulse spacing of the pulse signal to be measured.

2. 发明授权

US5828717A Time counting circuit and counter circuit 失效
标题翻译：计时电路和计数器电路
公开(公告)号：US5828717A
公开(公告)日：1998-10-27
申请号：US624960
申请日：1996-03-27
申请人： Keiichi Kusumoto , Shiro Dosho , Yutaka Terada , Akira Matsuzawa
发明人： Keiichi Kusumoto , Shiro Dosho , Yutaka Terada , Akira Matsuzawa
IPC分类号： G01R29/027 , G01C21/00
CPC分类号： G01R29/0273
摘要： There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption. An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition. A time-difference operating circuit corrects the numeric data outputted from the signal converting circuit based on the number of circulations of signal transition outputted from the counter circuit to provide time data, while calculating and outputting the pulse spacing of the pulse signal to be measured.
摘要翻译：提供了一种用于以高精度和低功耗测量脉冲信号的脉冲间隔的时间计数电路。由连接在环上的奇数个反相器组成的逆变器环振荡，并且一个信号转换发生在似乎在逆变器环周围似乎循环。连接到构成逆变器环的逆变器的各个输出端子的保持电路在待测脉冲信号的上升沿同时输出从逆变器输出的信号。然后，输出的信号由信号转换电路转换成数字数据。连接到构成逆变器环的逆变器之一的输出端的计数器电路对信号转换的循环数进行计数。时差操作电路根据从计数器电路输出的信号转换的循环数来校正从信号转换电路输出的数字数据，以提供时间数据，同时计算并输出要测量的脉冲信号的脉冲间隔。

3. 发明授权

US5982841A Time counting circuit, pulse converting circuit and FM demodulating circuit 失效
标题翻译：时间计数电路，脉冲转换电路和FM解调电路
公开(公告)号：US5982841A
公开(公告)日：1999-11-09
申请号：US747180
申请日：1996-11-12
申请人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
发明人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
IPC分类号： G01R29/027 , H03D3/04 , H03K9/06 , H03M1/50 , G01M3/00
CPC分类号： G04F10/005 , G01R29/027 , H03D3/04 , H03K9/06
摘要： Provided is a time counting circuit which can measure the time taken from the rising edge to the falling edge of a pulse signal and the time from the falling edge to the rising edge thereof. The time counting circuit according to the present invention comprises a measuring circuit for measuring the time between either of the rising and falling edges of the pulse signal, and a pulse converting circuit for converting a pulse signal to be measured to a pulse signal having either of the edges in accordance with the rising edge of the pulse signal to be measured and having either of the edges in accordance with the falling edge of the pulse signal to be measured. The time between either of the edges of the pulse signal converted by the pulse converting circuit is measured by the measuring circuit. The time obtained by measurement is the time taken from the rising edge to the falling edge of the pulse signal to be measured or the time taken from the falling edge to the rising edge thereof.
摘要翻译：提供了一种时间计数电路，其可以测量从脉冲信号的上升沿到下降沿的时间以及从下降沿到上升沿的时间。根据本发明的计时电路包括：测量脉冲信号的上升沿和下降沿之间的时间的测量电路;以及脉冲转换电路，用于将要测量的脉冲信号转换成具有根据要测量的脉冲信号的上升沿的边缘，并根据要测量的脉冲信号的下降沿具有任一边缘。由脉冲转换电路转换的脉冲信号的任一边之间的时间由测量电路测量。通过测量获得的时间是从要测量的脉冲信号的上升沿到下降沿或从下降沿到其上升沿的时间所花费的时间。

4. 发明授权

US5717624A Analog memory circuit and method for recording analog signal 失效
标题翻译：模拟记忆电路和记录模拟信号的方法
公开(公告)号：US5717624A
公开(公告)日：1998-02-10
申请号：US739867
申请日：1996-10-31
申请人： Keiichi Kusumoto , Kenji Murata , Yutaka Terada , Akira Matsuzawa
发明人： Keiichi Kusumoto , Kenji Murata , Yutaka Terada , Akira Matsuzawa
IPC分类号： G11C27/02 , G11C27/00
CPC分类号： G11C27/026
摘要： An analog memory circuit of the present invention includes: a recording circuit for recording and holding an input analog signal as a charge and for reading out the analog signal after deterioration of the analog signal caused by leakage of the charge in a holding operation is eliminated; a selecting circuit for controlling an operation of the recording circuit; and a driving circuit for supplying a predetermined constant voltage to the recording circuit, wherein the recording circuit includes: an input/output terminal for inputting and outputting the analog signal; a first capacitor having a first electrode and a second electrode, for recording and holding the analog signal as the charge; and a second capacitor connected between the second electrode of the first capacitor and a reference potential, for holding a charge leaked from the first capacitor, and wherein an amount of charge corresponding to an amount of leaked charge held in the second capacitor is restored to the first capacitor with predetermined timing.
摘要翻译：本发明的模拟存储器电路包括：记录电路，用于记录和保持作为电荷的输入模拟信号，并且用于在由保持操作中的电荷泄漏引起的模拟信号劣化后读出模拟信号; 用于控制记录电路的操作的选择电路; 以及用于向所述记录电路提供预定的恒定电压的驱动电路，其中所述记录电路包括：用于输入和输出所述模拟信号的输入/输出端子; 具有第一电极和第二电极的第一电容器，用于记录和保持模拟信号作为电荷; 以及连接在第一电容器的第二电极和参考电位之间的第二电容器，用于保持从第一电容器泄漏的电荷，并且其中对应于保持在第二电容器中的泄漏电荷量的电荷量恢复到具有预定定时的第一电容器。

5. 发明授权

US5999586A Time counting circuit and pulse signal generating method 失效
标题翻译：时间计数电路和脉冲信号产生方法
公开(公告)号：US5999586A
公开(公告)日：1999-12-07
申请号：US795907
申请日：1997-03-04
申请人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
发明人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
IPC分类号： G01D3/00
CPC分类号： G01D3/00
摘要： There is provided a small-size time counting circuit which measures time with high accuracy and low power consumption. Around a differential inverter ring composed of an odd number of differential inverters of identical structure connected in a ring configuration, signal transition is caused to circulate by oscillation. A first signal group is composed of normal output signals from the odd-numbered differential inverters and inverted output signals from the even-numbered differential inverters, which rise and fall sequentially at equal time intervals corresponding to delay times in the individual differential inverters. A second signal group is composed of inverted output signals from the odd-numbered differential inverters and normal output signals from the even-numbered differential inverters, which similarly rise and fall sequentially at equal time intervals. Accordingly, even when the rise time of an output signal from each of the differential inverters composing the differential inverter ring is different from the fall time thereof, the use of the first and second signal groups provides equal increments of time for time measurement.
摘要翻译：提供了一种小型时间计数电路，以高精度和低功耗测量时间。围绕由具有相同结构的奇数差分逆变器组成的差动逆变器环以环形结构连接，使信号转变通过振荡循环。第一信号组由来自奇数编号的差分逆变器的正常输出信号和来自偶数编号的差分逆变器的反相输出信号组成，其以与各个差分逆变器中的延迟时间相对应的等时间间隔顺序上升和下降。第二信号组由来自奇数编号的差分逆变器的反相输出信号和来自偶数编号差动逆变器的正常输出信号组成，其类似地以相等的时间间隔顺序地上升和下降。因此，即使来自构成差分逆变器环的各差分逆变器的输出信号的上升时间与其下降时间不同，所以使用第一和第二信号组提供相等的时间测量时间。

6. 发明授权

US06172557B2 Time counting circuit, pulse converting circuit and FM demodulating circuit 失效
标题翻译：时间计数电路，脉冲转换电路和FM解调电路
公开(公告)号：US06172557B2
公开(公告)日：2001-01-09
申请号：US09398817
申请日：1999-09-20
申请人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
发明人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
IPC分类号： H03D300
CPC分类号： G04F10/005 , G01R29/027 , H03D3/04 , H03K9/06
摘要： Provided is a time counting circuit which can measure the time taken from the rising edge to the falling edge of a pulse signal and the time from the falling edge to the rising edge thereof. The time counting circuit according to the present invention comprises a measuring circuit for measuring the time between either of the rising and falling edges of the pulse signal, and a pulse converting circuit for converting a pulse signal to be measured to a pulse signal having either of the edges in accordance with the rising edge of the pulse signal to be measured and having either of the edges in accordance with the falling edge of the pulse signal to be measured. The time between either of the edges of the pulse signal converted by the pulse converting circuit is measured by the measuring circuit. The time obtained by measurement is the time taken from the rising edge to the falling edge of the pulse signal to be measured or the time taken from the falling edge to the rising edge thereof.
摘要翻译：提供了一种时间计数电路，其可以测量从脉冲信号的上升沿到下降沿的时间以及从下降沿到上升沿的时间。根据本发明的计时电路包括：测量脉冲信号的上升沿和下降沿之间的时间的测量电路;以及脉冲转换电路，用于将要测量的脉冲信号转换成具有根据要测量的脉冲信号的上升沿的边缘，并根据要测量的脉冲信号的下降沿具有任一边缘。由脉冲转换电路转换的脉冲信号的任一边之间的时间由测量电路测量。通过测量获得的时间是从要测量的脉冲信号的上升沿到下降沿或从下降沿到其上升沿的时间所花费的时间。

7. 发明授权

US5550544A Signal converter, noise shaper, AD converter and DA converter 失效
标题翻译：信号转换器，噪声整形器，AD转换器和DA转换器
公开(公告)号：US5550544A
公开(公告)日：1996-08-27
申请号：US200493
申请日：1994-02-23
申请人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Shono , Akira Matsuzawa
发明人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Shono , Akira Matsuzawa
IPC分类号： H03M3/00 , H03M1/00
CPC分类号： H03M3/424 , H03M3/456
摘要： The present invention provides a first-order delta-sigma AD converter adapted to conduct noise shaping and having a quantizer arranged such that, when the amplitude of an input signal entered into the quantizer is small, the amplitude of a difference signal between the input signal entered into the quantizer and an output signal therefrom, is small. It is therefore possible to achieve an efficient AD- or DA-converter reduced in power consumption, which satisfies the transmission characteristics of the specifications of CCITT G.714 based on a method of PCM-encoding an audio frequency band signal stipulated in the specifications of CCITT G.711.
摘要翻译：本发明提供了一种适用于进行噪声整形并具有量化器的一级Δ-ΣAD转换器，其被布置为使得当输入到量化器的输入信号的幅度较小时，输入信号之间的差信号的幅度进入量化器并且其输出信号很小。因此，可以实现功率消耗降低的有效的AD转换器或DA转换器，该功率消耗满足CCITT G.714的规格的传输特性，该方法基于对编码 CCITT G.711。

8. 发明授权

US06424184B1 FREQUENCY-VOLTAGE CONVERSION CIRCUIT, DELAY AMOUNT JUDGEMENT CIRCUIT, SYSTEM HAVING FREQUENCY-VOLTAGE CONVERSION CIRCUIT, METHOD OF ADJUSTING INPUT/OUTPUT CHARACTERISTICS OF FREQUENCY-VOLTAGE CONVERSION CIRCUIT, AND APPARATUS FOR AUTOMATICALLY ADJUSTING INPUT 失效
标题翻译：频率转换电路，延迟量判定电路，具有电压转换电路的系统，调整频率转换电路的输入/输出特性的方法以及用于自动调整输入的装置
公开(公告)号：US06424184B1
公开(公告)日：2002-07-23
申请号：US09269315
申请日：1999-03-24
申请人： Akira Yamamoto , Shiro Sakiyama , Hiroyuki Nakahira , Masaru Fukuda , Akira Matsuzawa , Shiro Dosho , Shinichi Yamamoto
发明人： Akira Yamamoto , Shiro Sakiyama , Hiroyuki Nakahira , Masaru Fukuda , Akira Matsuzawa , Shiro Dosho , Shinichi Yamamoto
IPC分类号： H03D300
CPC分类号： G01R23/06 , G06F1/3203 , Y02D10/126
摘要： A frequency-voltage conversion circuit 21 receives a clock CLK as an input and provides a voltage IVdd in accordance with the frequency of the clock as an output. The input and output characteristic of the frequency-voltage conversion circuit 21 is adjusted to substantially match a given input and output characteristic.
摘要翻译：频率电压转换电路21接收时钟CLK作为输入，并根据时钟的频率提供电压IVdd作为输出。频率电压转换电路21的输入和输出特性被调节以基本匹配给定的输入和输出特性。

9. 发明授权

US5699064A Oversampling D/A converter using a bidirectional shift register 失效
标题翻译：使用双向移位寄存器的过采样D / A转换器
公开(公告)号：US5699064A
公开(公告)日：1997-12-16
申请号：US509665
申请日：1995-07-31
申请人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , George Hayashi , Seizo Inagaki , Akira Matsuzawa
发明人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , George Hayashi , Seizo Inagaki , Akira Matsuzawa
IPC分类号： H03M3/04 , H03M1/78
CPC分类号： H03M3/376 , H03M3/50
摘要： In an interpolative modulator, a signal which varies by only .+-.1 with one clock from a 1-bit quantizer is used as a shift-direction control signal. The shift-direction control signal is given to a bidirectional shift register. The bidirectional shift register shifts data based on the value of the shift-direction control signal that has been received. The output from the bidirectional shift register is given as a control signal to a resistive-ladder-type D/A converter. The resistive-ladder-type D/A converter outputs an analog potential corresponding to a switch selected by the above control signal. Therefore, if a delay difference occurs between any two bits, two adjacent switches are simply selected simultaneously, so that the output from the resistive-ladder-type D/A converter varies continuously. Consequently, there can be provided an oversampling D/A converter of resistive-ladder type with high accuracy and an increased yield, which is free from glitch (transiently generated noise).
摘要翻译：在内插调制器中，使用从1比特量化器的一个时钟仅变化+/- 1的信号作为移位方向控制信号。移位方向控制信号被提供给双向移位寄存器。双向移位寄存器基于接收到的移位方向控制信号的值来移位数据。来自双向移位寄存器的输出作为电阻梯型D / A转换器的控制信号给出。电阻梯型D / A转换器输出与由上述控制信号选择的开关相对应的模拟电位。因此，如果任意两位之间发生延迟差，则两个相邻的开关被简单地同时选择，使得电阻梯型D / A转换器的输出连续变化。因此，可以提供具有高精度和增加的产量的电梯梯型的过采样D / A转换器，其没有毛刺（瞬时产生的噪声）。

10. 发明授权

US5920209A Time counting circuit, sampling circuit, skew adjusting circuit, and logic analyzing circuit 失效
公开(公告)号：US5920209A
公开(公告)日：1999-07-06
申请号：US99455
申请日：1998-06-18
申请人： Keiichi Kusumoto , Akira Matsuzawa
发明人： Keiichi Kusumoto , Akira Matsuzawa
IPC分类号： G01R23/10 , G01R29/02 , G06F1/10 , G06F11/25 , H03K23/00 , H03K23/54 , H03M1/50 , H03M1/64 , H03K19/0175
CPC分类号： G04F10/005 , G01R29/02 , G06F1/10 , G06F11/25
摘要： There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal. A row of holding circuits consists of a plurality of holding circuits connected to the output terminals of the respective sampling circuits and holds the output signals from the sampling circuits in response to a direction indicated by the second switch signal. An operating circuit calculates the pulse spacing of the pulse signal to be measured based on a logic level signal outputted from the row of holding circuits.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式