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1. 发明申请

US20100027352A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100027352A1
公开(公告)日：2010-02-04
申请号：US12489870
申请日：2009-06-23
申请人： Masayoshi NAKAYAMA , Kazuyuki Kouno , Reiji Mochida , Hoshihide Haruyama
发明人： Masayoshi NAKAYAMA , Kazuyuki Kouno , Reiji Mochida , Hoshihide Haruyama
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/344 , G11C16/3445
摘要： In a non-volatile semiconductor memory device, variations in voltage applied to a bit line when an erase voltage applying step is repeatedly executed are suppressed, thereby reducing variations in Vt after erasure. A memory array includes memory cells arranged in an array, a plurality of word lines, and a plurality of bit lines and main bit lines. The memory array also includes a usable region which can store data and an isolation region which cannot store data. Each bit line provided in the usable region is connected via a select transistor to the corresponding main bit line. At least one main bit line is connected not only to a bit line of the usable region, but also to a bit line of the isolation region via a select transistor.
摘要翻译：在非易失性半导体存储器件中，抑制了当擦除电压施加步骤被重复执行时施加到位线的电压变化，从而减少了擦除后Vt的变化。存储器阵列包括以阵列布置的存储器单元，多个字线以及多个位线和主位线。存储器阵列还包括可存储数据的可用区域和不能存储数据的隔离区域。提供在可用区域中的每个位线通过选择晶体管连接到相应的主位线。至少一个主位线不仅连接到可用区域的位线，而且还经由选择晶体管连接到隔离区域的位线。

2. 发明授权

US08014202B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08014202B2
公开(公告)日：2011-09-06
申请号：US12489870
申请日：2009-06-23
申请人： Masayoshi Nakayama , Kazuyuki Kouno , Reiji Mochida , Hoshihide Haruyama
发明人： Masayoshi Nakayama , Kazuyuki Kouno , Reiji Mochida , Hoshihide Haruyama
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/16 , G11C16/344 , G11C16/3445
摘要： In a non-volatile semiconductor memory device, variations in voltage applied to a bit line when an erase voltage applying step is repeatedly executed are suppressed, thereby reducing variations in Vt after erasure. A memory array includes memory cells arranged in an array, a plurality of word lines, and a plurality of bit lines and main bit lines. The memory array also includes a usable region which can store data and an isolation region which cannot store data. Each bit line provided in the usable region is connected via a select transistor to the corresponding main bit line. At least one main bit line is connected not only to a bit line of the usable region, but also to a bit line of the isolation region via a select transistor.
摘要翻译：在非易失性半导体存储器件中，抑制了当擦除电压施加步骤被重复执行时施加到位线的电压变化，从而减少了擦除后Vt的变化。存储器阵列包括以阵列布置的存储器单元，多个字线以及多个位线和主位线。存储器阵列还包括可存储数据的可用区域和不能存储数据的隔离区域。提供在可用区域中的每个位线通过选择晶体管连接到相应的主位线。至少一个主位线不仅连接到可用区域的位线，而且还经由选择晶体管连接到隔离区域的位线。

3. 发明授权

US07924627B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07924627B2
公开(公告)日：2011-04-12
申请号：US12488867
申请日：2009-06-22
申请人： Kazuyuki Kouno , Hoshihide Haruyama , Masayoshi Nakayama , Reiji Mochida
发明人： Kazuyuki Kouno , Hoshihide Haruyama , Masayoshi Nakayama , Reiji Mochida
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C8/10 , G11C16/0475 , G11C16/10 , G11C16/24
摘要： In a semiconductor memory device, a voltage rise due to IR-DROP is suppressed which occurs when a ground voltage is applied to a memory cell during a program operation. Discharge transistors are provided between the ground and bit lines connected to the source and drain of the memory cell. The discharge transistors receive mutually independent discharge control signals which are generated and outputted from a DS decoder driver at the respective gates thereof. To the bit line which applies the ground voltage to the memory cell, the ground voltage can be set using the discharge transistor.
摘要翻译：在半导体存储器件中，当在编程操作期间将接地电压施加到存储器单元时，抑制由于IR-DROP引起的电压上升。放电晶体管设置在连接到存储单元的源极和漏极的接地和位线之间。放电晶体管接收相互独立的放电控制信号，这些放电控制信号在DS解码器驱动器的相应门处产生和输出。对于将接地电压施加到存储单元的位线，可以使用放电晶体管来设置接地电压。

4. 发明申请

US20100027366A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100027366A1
公开(公告)日：2010-02-04
申请号：US12488867
申请日：2009-06-22
申请人： Kazuyuki KOUNO , Hoshihide Haruyama , Masayoshi Nakayama , Reiji Mochida
发明人： Kazuyuki KOUNO , Hoshihide Haruyama , Masayoshi Nakayama , Reiji Mochida
IPC分类号： G11C5/14
CPC分类号： G11C8/10 , G11C16/0475 , G11C16/10 , G11C16/24
摘要： In a semiconductor memory device, a voltage rise due to IR-DROP is suppressed which occurs when a ground voltage is applied to a memory cell during a program operation. Discharge transistors are provided between the ground and bit lines connected to the source and drain of the memory cell. The discharge transistors receive mutually independent discharge control signals which are generated and outputted from a DS decoder driver at the respective gates thereof. To the bit line which applies the ground voltage to the memory cell, the ground voltage can be set using the discharge transistor.
摘要翻译：在半导体存储器件中，当在编程操作期间将接地电压施加到存储器单元时，抑制由于IR-DROP引起的电压上升。放电晶体管设置在连接到存储单元的源极和漏极的接地和位线之间。放电晶体管接收相互独立的放电控制信号，这些放电控制信号在DS解码器驱动器的相应门处产生和输出。对于将接地电压施加到存储单元的位线，可以使用放电晶体管来设置接地电压。

5. 发明申请

US20130003463A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20130003463A1
公开(公告)日：2013-01-03
申请号：US13608587
申请日：2012-09-10
申请人： Masayoshi Nakayama , Takashi Ono , Reiji Mochida
发明人： Masayoshi Nakayama , Takashi Ono , Reiji Mochida
IPC分类号： G11C16/12 , G11C16/04
CPC分类号： G11C16/0491 , G11C16/0408 , G11C16/0475 , G11C16/06 , G11C16/10
摘要： Bit lines connected to each nonvolatile memory cell are selected by corresponding selective transistors. A first drive circuit for driving the gate of one of the selective transistors receives a voltage selected by a first voltage switch, and a second drive circuit for driving the gate of the other selective transistor receives a voltage selected by a second voltage switch. A transistor constituting the first drive circuit is different in structure from a transistor constituting the second drive circuit.
摘要翻译：连接到每个非易失性存储单元的位线由相应的选择晶体管选择。用于驱动选择晶体管之一的栅极的第一驱动电路接收由第一电压开关选择的电压，并且用于驱动另一个选择晶体管的栅极的第二驱动电路接收由第二电压开关选择的电压。构成第一驱动电路的晶体管的结构与构成第二驱动电路的晶体管的结构不同。

6. 发明授权

US08711629B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08711629B2
公开(公告)日：2014-04-29
申请号：US13608587
申请日：2012-09-10
申请人： Masayoshi Nakayama , Takashi Ono , Reiji Mochida
发明人： Masayoshi Nakayama , Takashi Ono , Reiji Mochida
IPC分类号： G11C16/24
CPC分类号： G11C16/0491 , G11C16/0408 , G11C16/0475 , G11C16/06 , G11C16/10
摘要： Bit lines connected to each nonvolatile memory cell are selected by corresponding selective transistors. A first drive circuit for driving the gate of one of the selective transistors receives a voltage selected by a first voltage switch, and a second drive circuit for driving the gate of the other selective transistor receives a voltage selected by a second voltage switch. A transistor constituting the first drive circuit is different in structure from a transistor constituting the second drive circuit.
摘要翻译：连接到每个非易失性存储单元的位线由相应的选择晶体管选择。用于驱动选择晶体管之一的栅极的第一驱动电路接收由第一电压开关选择的电压，并且用于驱动另一个选择晶体管的栅极的第二驱动电路接收由第二电压开关选择的电压。构成第一驱动电路的晶体管的结构与构成第二驱动电路的晶体管的结构不同。

7. 发明授权

US08593888B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08593888B2
公开(公告)日：2013-11-26
申请号：US13591766
申请日：2012-08-22
申请人： Reiji Mochida , Takafumi Maruyama , Yukimasa Hamamoto
发明人： Reiji Mochida , Takafumi Maruyama , Yukimasa Hamamoto
IPC分类号： G11C5/14
CPC分类号： G11C16/30 , G11C16/10 , G11C16/26
摘要： In a semiconductor memory device, the output of a regulator is coupled to the inputs of first and second switches, the output of the first switch is coupled to a path for supplying the drain voltage of a memory cell in the first mode, and the output of the second switch is coupled to a path for supplying the gate voltage of the memory cell in the second mode. A fourth switch is placed in parallel with the second switch: the output of the fourth switch is coupled to the output of the second switch, to supply the gate voltage of the memory cell in the first mode. Thus, one regulator is used as both the regulator for the drain voltage of the memory cell and the regulator for the gate voltage of the memory cell.
摘要翻译：在半导体存储器件中，调节器的输出耦合到第一和第二开关的输入，第一开关的输出耦合到用于在第一模式中提供存储单元的漏极电压的路径，并且输出的第二开关耦合到用于在第二模式中提供存储器单元的栅极电压的路径。第四开关与第二开关并联放置：第四开关的输出耦合到第二开关的输出，以在第一模式中提供存储单元的栅极电压。因此，一个调节器用作存储器单元的漏极电压的调节器和用于存储器单元的栅极电压的调节器。

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