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    • 8. 发明申请
    • IMAGE FORMING APPARATUS AND METHOD OF CONTROLLING DEVELOPMENT ELECTRIC FIELD STRENGTH THEREIN
    • 图像形成装置及控制发明电场强度的方法
    • US20100215389A1
    • 2010-08-26
    • US12709034
    • 2010-02-19
    • Masaaki IMAHORIMasayoshi NAKAYAMA
    • Masaaki IMAHORIMasayoshi NAKAYAMA
    • G03G15/06
    • G03G15/065G03G15/55G03G15/553G03G2215/0129
    • An image forming apparatus includes an image carrier, a developer carrier, a runout measurement information storage unit to store runout measurement information of the image carrier and the developer carrier, including runout amounts on the circumference of the image and developer carriers in a development area, a development gap measurement information storage unit to store information obtained by measuring a development gap when runout measurement points of the image and developer carriers face each other, and a development electric field strength control unit to obtain each development electric field strength based on the runout measurement information and the development gap measurement information, and determine control contents of development electric field strength control to cause the entire development electric field strengths to fall within an acceptable range of a target electric field strength to perform the control contents.
    • 图像形成装置包括图像载体,显影剂载体,跳动测量信息存储单元,用于存储图像载体和显影剂载体的跳动测量信息,包括在显影区域中的图像和显影剂载体的圆周上的偏移量, 显影间隙测量信息存储单元,用于存储当图像和显影剂载体的跳动测量点彼此面对时通过测量显影间隙获得的信息;以及显影电场强度控制单元,用于基于跳动测量获得每个显影电场强度 信息和开发间隙测量信息,并且确定开发电场强度控制的控制内容以使整个显影电场强度落入目标电场强度的可接受范围内,以执行控制内容。
    • 9. 发明授权
    • Nonvolatile semiconductor storage apparatus and method of driving the same
    • 非易失性半导体存储装置及其驱动方法
    • US07339823B2
    • 2008-03-04
    • US11544608
    • 2006-10-10
    • Masayoshi NakayamaAsako MiyoshiSeiji Yamahira
    • Masayoshi NakayamaAsako MiyoshiSeiji Yamahira
    • G11C11/34
    • G11C16/32G11C11/5642G11C16/26G11C2211/5641
    • A memory cell array is logically divided into a plurality of regions having different reading speeds, the respective regions having the different reading speeds include region information storage regions for storing region information in which at least two addresses present in the memory cell at the same time are set to be different regions, a reading control circuit is constituted to carry out a reading operation by determining any of the divided regions which is to be read, selecting an optimum reading method and controlling the reading circuit based on the region information stored in the region information storage region, and an address which can be read in a short time in multivalued information stored in one memory cell is set to be a high speed reading region and is distinguished from regions having the other reading speeds. Consequently, it is possible to efficiently write and read information of 2 bits or more in one memory cell array without reducing a using efficiency of the memory cell array.
    • 存储单元阵列在逻辑上被划分为具有不同读取速度的多个区域,具有不同读取速度的各个区域包括区域信息存储区域,用于存储其中同时存在于存储单元中的至少两个地址的区域信息 设置为不同的区域,读取控制电路被构成为通过确定要被读取的任何划分区域,选择最佳读取方法和基于存储在该区域中的区域信息来控制读取电路来执行读取操作 信息存储区域和在一个存储单元中存储的多值信息中可以在短时间内读取的地址被设置为高速读取区域,并且区别于具有其他读取速度的区域。 因此,可以在不降低存储单元阵列的使用效率的情况下有效地在一个存储单元阵列中写入和读取2位或更多的信息。
    • 10. 发明申请
    • Nonvolatile semiconductor storage apparatus and method of driving the same
    • 非易失性半导体存储装置及其驱动方法
    • US20070086245A1
    • 2007-04-19
    • US11544608
    • 2006-10-10
    • Masayoshi NakayamaAsako MiyoshiSeiji Yamahira
    • Masayoshi NakayamaAsako MiyoshiSeiji Yamahira
    • G11C16/04
    • G11C16/32G11C11/5642G11C16/26G11C2211/5641
    • A memory cell array is logically divided into a plurality of regions having different reading speeds, the respective regions having the different reading speeds include region information storage regions for storing region information in which at least two addresses present in the memory cell at the same time are set to be different regions, a reading control circuit is constituted to carry out a reading operation by determining any of the divided regions which is to be read, selecting an optimum reading method and controlling the reading circuit based on the region information stored in the region information storage region, and an address which can be read in a short time in multivalued information stored in one memory cell is set to be a high speed reading region and is distinguished from regions having the other reading speeds. Consequently, it is possible to efficiently write and read information of 2 bits or more in one memory cell array without reducing a using efficiency of the memory cell array.
    • 存储单元阵列在逻辑上被划分为具有不同读取速度的多个区域,具有不同读取速度的各个区域包括区域信息存储区域,用于存储其中同时存在于存储单元中的至少两个地址的区域信息 设置为不同的区域,读取控制电路被构成为通过确定要被读取的任何划分区域,选择最佳读取方法和基于存储在该区域中的区域信息来控制读取电路来执行读取操作 信息存储区域和在一个存储单元中存储的多值信息中可以在短时间内读取的地址被设置为高速读取区域,并且区别于具有其他读取速度的区域。 因此,可以在不降低存储单元阵列的使用效率的情况下有效地在一个存储单元阵列中写入和读取2位或更多的信息。