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1. 发明授权

US5140546A Adder circuit apparatus 失效
标题翻译：加法器电路装置
公开(公告)号：US5140546A
公开(公告)日：1992-08-18
申请号：US531713
申请日：1990-05-31
申请人： Kazuyuki Ishikawa , Yukihiko Shimazu , Toshiki Fujiyama
发明人： Kazuyuki Ishikawa , Yukihiko Shimazu , Toshiki Fujiyama
IPC分类号： G06F7/50 , G06F7/506 , G06F7/508
CPC分类号： G06F7/508
摘要： An adder circuit includes a Manchester-carry-chain circuit which propagates a carry signal for each block consisting of plural bits, and a carry-look-ahead circuit which selects said carry signal in response to a carry propagation signal being generated by a full adder, and when the carry signal is not generated in the two consecutive blocks, an output from the Manchester-carry-chain circuit is selected by the carry-look-ahead circuit, so that the carry signal being inputted to the low-order block of the two blocks can be propagated as the carry signal to be outputted from the high-order block.
摘要翻译：一个加法器电路包括一个曼彻斯特携带链电路，它传播由多个比特组成的每个块的进位信号，以及一个进位前进电路，其响应于一个全加器产生的进位传播信号选择所述进位信号，并且当在两个连续块中不产生进位信号时，由进位查询电路选择来自曼彻斯特携带链电路的输出，使得进位信号被输入到低位块可以将这两个块作为从高阶块输出的进位信号传播。

2. 发明授权

US5361371A Microprocessor with reset execution from an arbitrary address 失效
标题翻译：微处理器从任意地址复位执行
公开(公告)号：US5361371A
公开(公告)日：1994-11-01
申请号：US966123
申请日：1992-10-22
申请人： Kohji Kawamoto , Yukihiko Shimazu , Toshiki Fujiyama
发明人： Kohji Kawamoto , Yukihiko Shimazu , Toshiki Fujiyama
IPC分类号： G06F9/06 , G06F9/26 , G06F9/32 , G06F9/445 , G06F15/78 , G06F9/22 , G06F9/312
CPC分类号： G06F9/268 , G06F9/32 , G06F9/321 , G06F9/445
摘要： A microprocessor which, following a reset signal, permits execution beginning from an arbitrary address. The microprocessor is constituted in a manner such that arbitrary data is set in advance in a data register as an address. The address in the data register is given to a program counter by a register indirect jump instruction which does not originate in the instruction ROM. The microprocessor has a resetting function in addition to the normal resetting function. The normal resetting function includes re-executing a program from a predetermined address, such as a zero address. The normal resetting function occurs in the case where the logical level of a control signal input terminal is a predetermined level at a point of time when the reset signal to the reset terminal is cleared. When the control signal is at a different level, the arbitrary data set in the data register is transferred to the program counter by the register indirect jump instruction and is set in the program counter. The program is then re-executed with that data set as an instruction start address.
摘要翻译：在复位信号之后，微处理器允许从任意地址开始执行。微处理器的构成是将任意数据预先设置在数据寄存器中作为地址。数据寄存器中的地址通过不在指令ROM中的寄存器间接跳转指令给予程序计数器。微处理器除正常的复位功能之外还具有复位功能。正常复位功能包括从诸如零地址的预定地址重新执行程序。在复位终端的复位信号清零的时刻，控制信号输入端子的逻辑电平为规定电平的情况下，发生通常的复位功能。当控制信号处于不同的电平时，通过寄存器间接跳转指令将数据寄存器中设置的任意数据传送到程序计数器，并在程序计数器中设置。然后，以该数据集作为指令开始地址重新执行该程序。

3. 发明授权

US5551045A Microprocessor with reset execution from an arbitrary address 失效
标题翻译：微处理器从任意地址复位执行
公开(公告)号：US5551045A
公开(公告)日：1996-08-27
申请号：US245985
申请日：1994-05-18
申请人： Kohji Kawamoto , Yukihiko Shimazu , Toshiki Fujiyama
发明人： Kohji Kawamoto , Yukihiko Shimazu , Toshiki Fujiyama
IPC分类号： G06F9/06 , G06F9/26 , G06F9/32 , G06F9/445 , G06F15/78 , G06F9/34
CPC分类号： G06F9/268 , G06F9/32 , G06F9/321 , G06F9/445
摘要： A microprocessor with a built-in instruction ROM is described. Arbitrary data is set in advance in a data register of the microprocessor. The arbitrary data is given to a program counter by a register indirect jump instruction. The microprocessor has a normal reset function and an additional reset function allowing reset from a predetermined address. The additional reset function is used when the logic level of a control signal input terminal is at a predetermined level when the reset signal to the reset terminal is cleared. The arbitrary data is transferred to the program counter by register indirect jump instruction and set in the program counter. The program is re-executed with this data as an instruction start address.
摘要翻译：描述具有内置指令ROM的微处理器。任意数据预先设置在微处理器的数据寄存器中。通过寄存器间接跳转指令将任意数据提供给程序计数器。微处理器具有正常复位功能和允许从预定地址复位的附加复位功能。当复位端子的复位信号清零时，当控制信号输入端子的逻辑电平处于预定电平时，使用附加复位功能。任意数据通过寄存器间接跳转指令传送到程序计数器，并在程序计数器中设置。使用该数据作为指令开始地址重新执行该程序。

4. 发明授权

US5122693A Clock system implementing divided power supply wiring 失效
标题翻译：时钟系统实现分电源接线
公开(公告)号：US5122693A
公开(公告)日：1992-06-16
申请号：US613187
申请日：1990-11-13
申请人： Nobuhiko Honda , Toyohiko Yoshida , Yukihiko Shimazu
发明人： Nobuhiko Honda , Toyohiko Yoshida , Yukihiko Shimazu
IPC分类号： G06F1/10 , H01L21/822 , H01L27/04 , H03K5/00
CPC分类号： G06F1/10
摘要： Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.
摘要翻译：可以通过将晶体管级从外部时钟的输入减少到内部时钟驱动级的输出而减小外部和内部时钟之间的相位差的集成电路，并且还可以减少当时钟驱动器驱动时产生的噪声高速地，内部时钟具有较大的负载，并且可以防止噪声传播到其它部分，以避免对其他电路造成不良影响，此外，具有相同相位的内部时钟可以提供给芯片的每个部分即使在高工作频率下，通过最小化芯片上的内部时钟信号的偏移，并且还可以通过消除内部时钟信号驱动器的通过电流来降低需求电流。

5. 发明授权

US4903005A Comparator circuit 失效
标题翻译：比较器电路
公开(公告)号：US4903005A
公开(公告)日：1990-02-20
申请号：US250461
申请日：1988-09-28
申请人： Narumi Sakashita , Yukihiko Shimazu
发明人： Narumi Sakashita , Yukihiko Shimazu
IPC分类号： G06F7/02
CPC分类号： G06F7/026
摘要： A multiple digit comparator checks the first and the second input data for a match. If the two input data match, the carry input data from the previous digit is outputted as the carry output data for the next digit; if the two input data do not match, then a no match signal is outputted as the carry output data for the next digit. Next, if the carry input data and the carry output data do not match then a change point signal is outputted. When this change point signal is outputted, the first and the second input data are outputted. This facilitates the design of a more regular comparator circuit layout and of a faster comparator circuit.
摘要翻译：多位数比较器检查第一和第二输入数据以进行匹配。如果两个输入数据相匹配，则前一个数字的进位输入数据作为下一个数字的进位输出数据输出; 如果两个输入数据不匹配，则输出不匹配信号作为下个数字的进位输出数据。接下来，如果进位输入数据和进位输出数据不匹配，则输出变化点信号。当输出该变化点信号时，输出第一和第二输入数据。这有助于设计更加规则的比较器电路布局和更快的比较器电路。

6. 发明申请

US20080288836A1 Semiconductor integrated circuit capable of testing with small scale circuit configuration 审中-公开
公开(公告)号：US20080288836A1
公开(公告)日：2008-11-20
申请号：US12219230
申请日：2008-07-17
申请人： Soichi Kobayashi , Yoshiaki Yamazaki , Yukihiko Shimazu
发明人： Soichi Kobayashi , Yoshiaki Yamazaki , Yukihiko Shimazu
IPC分类号： G11C29/00 , G06F11/277
CPC分类号： G11C29/848 , G11C11/41 , G11C29/44
摘要： In a test mode, a comparator compares for each column a value of data read from each memory cell connected to an activated word line with an expected value to be read from each memory cell. An error register holds error data based on a comparison result by a comparator. Each bit of the error data indicates the comparison result by the comparator for a corresponding column. Each bit is set to “0” when the comparison result for the corresponding column always indicates equality whichever word line is activated, and is set to “1” when once the comparison result for the corresponding column indicates difference.

7. 发明授权

US5936455A MOS integrated circuit with low power consumption 失效
标题翻译： MOS集成电路具有低功耗
公开(公告)号：US5936455A
公开(公告)日：1999-08-10
申请号：US611087
申请日：1996-03-05
申请人： Souichi Kobayashi , Yukihiko Shimazu , Toshio Kishi
发明人： Souichi Kobayashi , Yukihiko Shimazu , Toshio Kishi
IPC分类号： H01L21/8238 , G05F3/24 , G11C11/407 , H01L27/092 , H03K19/00 , H03K19/0175 , H03K19/0948 , H01L27/00
CPC分类号： G05F3/247
摘要： A MOS integrated circuit comprising a middle potential node to which a middle potential is to be supplied, a first operation circuit operating between a first potential and the middle potential, a second operation circuit operating between the middle potential and a second potential, and a node stabilization circuit for stabilizing the potential of the middle potential node.
摘要翻译：一种MOS集成电路，包括要提供中间电位的中间电位节点，在第一电位和中间电位之间运行的第一运算电路，在中间电位和第二电位之间运行的第二运算电路，以及节点稳定电路，用于稳定中间电位节点的电位。

8. 发明授权

US5051997A Semiconductor integrated circuit with self-test function 失效
标题翻译：具有自检功能的半导体集成电路
公开(公告)号：US5051997A
公开(公告)日：1991-09-24
申请号：US622316
申请日：1990-12-03
申请人： Narumi Sakashita , Yukihiko Shimazu
发明人： Narumi Sakashita , Yukihiko Shimazu
IPC分类号： G01R31/28 , G06F11/27 , H01L21/66 , H01L21/822 , H01L27/04
CPC分类号： G06F11/27
摘要： Apparatus is disclosed for a self-test function internal to a semiconductor integrated circuit. The invention includes an internal random number generator for generating test data for use by a self-test program. As a result of the invention, external equipment is not necessary for executing the self-test, internal memory for storing for self-test data can be decreased, and self-test can be performed readily by the user. Furthermore, since self-test result data is compressed so as to be compared with the data of prediction values, the data of the test result can be reduced for easy processing.
摘要翻译：公开了用于半导体集成电路内部的自检功能的装置。本发明包括一个内部随机数发生器，用于产生用于自检程序的测试数据。作为本发明的结果，外部设备不需要执行自检，可以减少用于自检数据的存储的内部存储器，并且用户可以容易地进行自检。此外，由于自检结果数据被压缩以便与预测值的数据进行比较，因此可以减少测试结果的数据以便于处理。

9. 发明授权

US4914616A Coded incrementer having minimal carry propagation delay 失效
标题翻译：具有最小进位传播延迟的编码增量器
公开(公告)号：US4914616A
公开(公告)日：1990-04-03
申请号：US131864
申请日：1987-12-11
申请人： Taketora Shiraishi , Yukihiko Shimazu
发明人： Taketora Shiraishi , Yukihiko Shimazu
IPC分类号： G06F7/50 , G06F7/505 , G06F7/506
CPC分类号： G06F7/5055
摘要： As the incrementer of the invention comprises a shift register for its lower order bits, while its higher bit portions are constructed in the same way as a conventional incrementer, the incrementer can give output signals directly to a memory and the like without the necessity of decoding the same, and the incrementer is free from carry propagation delay possibilities, which assures an improved rate of operation of the incrementer as a whole.
摘要翻译：由于本发明的增量器包括用于其较低阶位的移位寄存器，而其较高位部分以与常规增量器相同的方式构造，所以递增器可以将输出信号直接提供给存储器等而不需要解码相同，并且增量器没有进位传播延迟的可能性，这保证了整体上增量器的操作速率的提高。

10. 发明授权

US4777623A Semiconductor memory device having initialization transistor 失效
标题翻译：具有初始晶体管的半导体存储器
公开(公告)号：US4777623A
公开(公告)日：1988-10-11
申请号：US869653
申请日：1986-06-02
申请人： Yukihiko Shimazu , Eiichi Teraoka
发明人： Yukihiko Shimazu , Eiichi Teraoka
IPC分类号： G11C7/00 , G06F1/24 , G11C11/401 , G11C11/41 , H03K3/037 , H03K3/356 , G11C11/40
CPC分类号： H03K3/356095 , H03K3/35606
摘要： A memory circuit 14 comprises a MOS transistor 15 having its threshold voltage selected to be higher than the output voltage on the occasion of the ordinary operation. Consequently, the MOS transistor 15 is off on the occasion of the ordinary operation, and a ratio latch 4 performs the ordinary storing operation. Meanwhile, if the output voltage of the power source 12 is raised, the MOS transistor 15 turns on to pull down the potential of a data input line 6a to the ratio latch. Accordingly, the ratio latch 4 is forced to be set.
摘要翻译：存储电路14包括在正常操作时选择其阈值电压高于输出电压的MOS晶体管15。因此，在正常工作的情况下，MOS晶体管15截止，比例锁存器4进行普通存储操作。同时，如果电源12的输出电压升高，则MOS晶体管15导通，将数据输入线6a的电位下拉到比率锁存器。因此，比例闩锁4被强制设定。

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