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1. 发明授权

US5551045A Microprocessor with reset execution from an arbitrary address 失效
标题翻译：微处理器从任意地址复位执行
公开(公告)号：US5551045A
公开(公告)日：1996-08-27
申请号：US245985
申请日：1994-05-18
申请人： Kohji Kawamoto , Yukihiko Shimazu , Toshiki Fujiyama
发明人： Kohji Kawamoto , Yukihiko Shimazu , Toshiki Fujiyama
IPC分类号： G06F9/06 , G06F9/26 , G06F9/32 , G06F9/445 , G06F15/78 , G06F9/34
CPC分类号： G06F9/268 , G06F9/32 , G06F9/321 , G06F9/445
摘要： A microprocessor with a built-in instruction ROM is described. Arbitrary data is set in advance in a data register of the microprocessor. The arbitrary data is given to a program counter by a register indirect jump instruction. The microprocessor has a normal reset function and an additional reset function allowing reset from a predetermined address. The additional reset function is used when the logic level of a control signal input terminal is at a predetermined level when the reset signal to the reset terminal is cleared. The arbitrary data is transferred to the program counter by register indirect jump instruction and set in the program counter. The program is re-executed with this data as an instruction start address.
摘要翻译：描述具有内置指令ROM的微处理器。任意数据预先设置在微处理器的数据寄存器中。通过寄存器间接跳转指令将任意数据提供给程序计数器。微处理器具有正常复位功能和允许从预定地址复位的附加复位功能。当复位端子的复位信号清零时，当控制信号输入端子的逻辑电平处于预定电平时，使用附加复位功能。任意数据通过寄存器间接跳转指令传送到程序计数器，并在程序计数器中设置。使用该数据作为指令开始地址重新执行该程序。

2. 发明授权

US5361371A Microprocessor with reset execution from an arbitrary address 失效
标题翻译：微处理器从任意地址复位执行
公开(公告)号：US5361371A
公开(公告)日：1994-11-01
申请号：US966123
申请日：1992-10-22
申请人： Kohji Kawamoto , Yukihiko Shimazu , Toshiki Fujiyama
发明人： Kohji Kawamoto , Yukihiko Shimazu , Toshiki Fujiyama
IPC分类号： G06F9/06 , G06F9/26 , G06F9/32 , G06F9/445 , G06F15/78 , G06F9/22 , G06F9/312
CPC分类号： G06F9/268 , G06F9/32 , G06F9/321 , G06F9/445
摘要： A microprocessor which, following a reset signal, permits execution beginning from an arbitrary address. The microprocessor is constituted in a manner such that arbitrary data is set in advance in a data register as an address. The address in the data register is given to a program counter by a register indirect jump instruction which does not originate in the instruction ROM. The microprocessor has a resetting function in addition to the normal resetting function. The normal resetting function includes re-executing a program from a predetermined address, such as a zero address. The normal resetting function occurs in the case where the logical level of a control signal input terminal is a predetermined level at a point of time when the reset signal to the reset terminal is cleared. When the control signal is at a different level, the arbitrary data set in the data register is transferred to the program counter by the register indirect jump instruction and is set in the program counter. The program is then re-executed with that data set as an instruction start address.
摘要翻译：在复位信号之后，微处理器允许从任意地址开始执行。微处理器的构成是将任意数据预先设置在数据寄存器中作为地址。数据寄存器中的地址通过不在指令ROM中的寄存器间接跳转指令给予程序计数器。微处理器除正常的复位功能之外还具有复位功能。正常复位功能包括从诸如零地址的预定地址重新执行程序。在复位终端的复位信号清零的时刻，控制信号输入端子的逻辑电平为规定电平的情况下，发生通常的复位功能。当控制信号处于不同的电平时，通过寄存器间接跳转指令将数据寄存器中设置的任意数据传送到程序计数器，并在程序计数器中设置。然后，以该数据集作为指令开始地址重新执行该程序。

3. 发明授权

US5140546A Adder circuit apparatus 失效
标题翻译：加法器电路装置
公开(公告)号：US5140546A
公开(公告)日：1992-08-18
申请号：US531713
申请日：1990-05-31
申请人： Kazuyuki Ishikawa , Yukihiko Shimazu , Toshiki Fujiyama
发明人： Kazuyuki Ishikawa , Yukihiko Shimazu , Toshiki Fujiyama
IPC分类号： G06F7/50 , G06F7/506 , G06F7/508
CPC分类号： G06F7/508
摘要： An adder circuit includes a Manchester-carry-chain circuit which propagates a carry signal for each block consisting of plural bits, and a carry-look-ahead circuit which selects said carry signal in response to a carry propagation signal being generated by a full adder, and when the carry signal is not generated in the two consecutive blocks, an output from the Manchester-carry-chain circuit is selected by the carry-look-ahead circuit, so that the carry signal being inputted to the low-order block of the two blocks can be propagated as the carry signal to be outputted from the high-order block.
摘要翻译：一个加法器电路包括一个曼彻斯特携带链电路，它传播由多个比特组成的每个块的进位信号，以及一个进位前进电路，其响应于一个全加器产生的进位传播信号选择所述进位信号，并且当在两个连续块中不产生进位信号时，由进位查询电路选择来自曼彻斯特携带链电路的输出，使得进位信号被输入到低位块可以将这两个块作为从高阶块输出的进位信号传播。

4. 发明授权

US4908788A Shift control signal generation circuit for floating-point arithmetic operation 失效
标题翻译：用于浮点运算的移位控制信号发生电路
公开(公告)号：US4908788A
公开(公告)日：1990-03-13
申请号：US71739
申请日：1987-07-09
申请人： Toshiki Fujiyama
发明人： Toshiki Fujiyama
IPC分类号： G06F7/00 , G06F7/485 , G06F7/50 , G06F7/76
CPC分类号： G06F7/485
摘要： A logic circuit comprises a subtracter for receiving first and second binary data and outputting a difference between the first and second data, a decoder for outputting the output of the subtracter when the first data is greater than the second data and an inversion signal of the output from the subtracter when the second data is greater than the first data, and a shifter for outputting the output of the decoder without modification when the first data is greater than the second data and a shifted value of the output from the decoder when the second data is greater than the first data.
摘要翻译：逻辑电路包括用于接收第一和第二二进制数据并输出第一和第二数据之间的差的减法器，用于当第一数据大于第二数据时输出减法器的输出的解码器和输出的反相信号当所述第二数据大于所述第一数据时，从所述减法器输出所述解码器的输出;以及移位器，用于当所述第一数据大于所述第二数据时，不修改地输出所述解码器的输出;以及移位器，当所述第二数据大于第一个数据。

5. 发明授权

US5301137A Circuit for fixed point or floating point arithmetic operations 失效
标题翻译：固定点或浮点算术运算电路
公开(公告)号：US5301137A
公开(公告)日：1994-04-05
申请号：US47757
申请日：1993-04-14
申请人： Takahiro Matsuo , Toshiki Fujiyama , Toru Kengaku
发明人： Takahiro Matsuo , Toshiki Fujiyama , Toru Kengaku
IPC分类号： G06F7/487 , G06F7/52 , G06F7/53 , G06F7/57 , G06F9/30 , G06F9/302 , G06F9/318 , G06F17/10 , G06F7/38
CPC分类号： G06F7/483 , G06F9/3001 , G06F9/30145 , G06F9/30181
摘要： An operation circuit for performing either fixed or floating point mathematical operations, having a mode control function for a multiplier including a multiplier, an arithmetic logic unit (ALU) and a signal generating circuit. A signal specifying the operating mode of the ALU, either a fixed point mode or a floating point mode is used by the signal generating circuit for generating either a fixed point multiplication signal or a floating point multiplication signal to control the multiplier, respectively.
摘要翻译：一种用于执行固定或浮点数学运算的运算电路，具有用于包括乘法器的乘法器的模式控制功能，运算逻辑单元（ALU）和信号产生电路。信号发生电路使用指定ALU的操作模式的信号，即固定点模式或浮点模式，用于分别产生固定点乘法信号或浮点乘法信号以控制乘法器。

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