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1. 发明授权

US08189424B2 Semiconductor memory device having plurality of types of memories integrated on one chip 有权
标题翻译：具有集成在一个芯片上的多种类型的存储器的半导体存储器件
公开(公告)号：US08189424B2
公开(公告)日：2012-05-29
申请号：US12397711
申请日：2009-03-04
申请人： Kazuto Uehara , Toshifumi Watanabe , Shigefumi Ishiguro , Kazuyoshi Muraoka
发明人： Kazuto Uehara , Toshifumi Watanabe , Shigefumi Ishiguro , Kazuyoshi Muraoka
IPC分类号： G11C8/00
CPC分类号： G11C7/1027 , G11C7/1006 , G11C7/1039 , G11C11/005 , G11C2029/0411
摘要： A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memories. The semiconductor memory device further includes a control circuit that controls a timing of starting counting up addresses and a timing of storing read data in the first data latch circuit at the time of the clock synchronous burst read operation in accordance with the bank structure of the buffer memory as a read operation target.
摘要翻译：配置为执行时钟同步突发读取操作的半导体存储器件包括具有不同库结构的多个缓冲存储器，以及存储从多个缓冲存储器读取的读取数据的第一和第二数据锁存电路。半导体存储装置还包括控制电路，其根据缓冲器的存储体结构，在时钟同步脉冲串读取操作时控制开始计数上升地址的定时和在第一数据锁存电路中存储读取数据的定时存储器作为读操作目标。

2. 发明申请

US20090316494A1 SEMICONDUCTOR MEMORY DEVICE HAVING PLURALITY OF TYPES OF MEMORIES INTEGRATED ON ONE CHIP 有权
标题翻译：具有集成在一个芯片上的多种类型的记忆体的半导体存储器件
公开(公告)号：US20090316494A1
公开(公告)日：2009-12-24
申请号：US12397711
申请日：2009-03-04
申请人： Kazuto UEHARA , Toshifumi Watanabe , Shigefumi Ishiguro , Kazuyoshi Muraoka
发明人： Kazuto UEHARA , Toshifumi Watanabe , Shigefumi Ishiguro , Kazuyoshi Muraoka
IPC分类号： G11C7/10 , G11C8/18 , G11C7/00
CPC分类号： G11C7/1027 , G11C7/1006 , G11C7/1039 , G11C11/005 , G11C2029/0411
摘要： A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memories. The semiconductor memory device further includes a control circuit that controls a timing of starting counting up addresses and a timing of storing read data in the first data latch circuit at the time of the clock synchronous burst read operation in accordance with the bank structure of the buffer memory as a read operation target.
摘要翻译：配置为执行时钟同步突发读取操作的半导体存储器件包括具有不同库结构的多个缓冲存储器，以及存储从多个缓冲存储器读取的读取数据的第一和第二数据锁存电路。半导体存储装置还包括控制电路，其根据缓冲器的存储体结构，在时钟同步脉冲串读取操作时控制开始计数上升地址的定时和在第一数据锁存电路中存储读取数据的定时存储器作为读操作目标。

3. 发明授权

US08223569B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08223569B2
公开(公告)日：2012-07-17
申请号：US12836851
申请日：2010-07-15
申请人： Tomoyuki Hamano , Shigefumi Ishiguro , Toshifumi Watanabe , Kazuto Uehara
发明人： Tomoyuki Hamano , Shigefumi Ishiguro , Toshifumi Watanabe , Kazuto Uehara
IPC分类号： G11C7/00
CPC分类号： G11C8/04 , G11C11/41 , G11C2029/0411
摘要： According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.
摘要翻译：根据一个实施例，半导体存储器件包括存储器阵列，地址计数器，地址检测电路和控制电路。存储器阵列具有布置在字线和位线的交叉位置处的多个存储单元。地址计数器与时钟同步地增加包括行地址和列地址的地址，以顺序输出递增的地址。地址检测电路在从地址计数器输出的地址处检测包括行地址切换到的行地址的地址，以输出检测信号。控制电路根据从地址检测电路输出的检测信号对与存储单元连接的位线执行预充电操作。

4. 发明授权

US08259523B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08259523B2
公开(公告)日：2012-09-04
申请号：US12836944
申请日：2010-07-15
申请人： Toshifumi Watanabe , Tomoyuki Hamano , Shigefumi Ishiguro , Kazuto Uehara
发明人： Toshifumi Watanabe , Tomoyuki Hamano , Shigefumi Ishiguro , Kazuto Uehara
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C8/12 , G11C11/005
摘要： According to one embodiment, a semiconductor memory device includes a first memory, a second memory and a control circuit. The first memory includes a first bank number. The second memory includes a second bank number larger than the first bank number. The control circuit controls a precharge operation with respect to bit lines provided in the first and second memories. When performing, with respect to the first memory, a synchronous operation that is effected in synchronization with a clock, the control circuit changes over a second precharge operation to an operation time different from a first precharge operation during a period from the end of the initial first precharge operation to the start of the subsequent second precharge operation after receiving an address.
摘要翻译：根据一个实施例，半导体存储器件包括第一存储器，第二存储器和控制电路。第一存储器包括第一个银行号码。第二存储器包括大于第一存储体号的第二存储体号。控制电路相对于设置在第一和第二存储器中的位线控制预充电操作。当相对于第一存储器执行与时钟同步地进行的同步操作时，控制电路在初始化结束时间段内将第二预充电操作改变为与第一预充电操作不同的操作时间在接收地址之后的第二预充电操作开始的第一预充电操作。

5. 发明申请

US20110013472A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20110013472A1
公开(公告)日：2011-01-20
申请号：US12836851
申请日：2010-07-15
申请人： Tomoyuki HAMANO , Shigefumi Ishiguro , Toshifumi Watanabe , Kazuto Uehara
发明人： Tomoyuki HAMANO , Shigefumi Ishiguro , Toshifumi Watanabe , Kazuto Uehara
IPC分类号： G11C8/00 , G11C8/04
CPC分类号： G11C8/04 , G11C11/41 , G11C2029/0411
摘要： According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.
摘要翻译：根据一个实施例，半导体存储器件包括存储器阵列，地址计数器，地址检测电路和控制电路。存储器阵列具有布置在字线和位线的交叉位置处的多个存储单元。地址计数器与时钟同步地增加包括行地址和列地址的地址，以顺序输出递增的地址。地址检测电路在从地址计数器输出的地址处检测包括行地址切换到的行地址的地址，以输出检测信号。控制电路根据从地址检测电路输出的检测信号对与存储单元连接的位线执行预充电操作。

6. 发明授权

US07577058B2 Semiconductor device having input detection circuit which operates in a synchronous operation and an asynchronous operation 失效
标题翻译：具有输入检测电路的半导体器件，其在同步操作和异步操作中工作
公开(公告)号：US07577058B2
公开(公告)日：2009-08-18
申请号：US11774919
申请日：2007-07-09
申请人： Toshifumi Watanabe , Shigefumi Ishiguro
发明人： Toshifumi Watanabe , Shigefumi Ishiguro
IPC分类号： G11C8/00
CPC分类号： H03K19/017509 , H03K5/19
摘要： A semiconductor device includes a first input terminal, the first input terminal being supplied with an input signal, an input detection circuit including a delay circuit having a second input terminal and an output terminal, the input detection circuit detecting a shift in the input signal and generating a first pulse signal in response to the shift, the input detection circuit being connected to the first input terminal, and a control circuit for generating control signals, each of the control signals being generated in response to a synchronous operation or an asynchronous operation respectively.
摘要翻译：一种半导体器件，包括：第一输入端子，第一输入端子被提供有输入信号;输入检测电路，包括具有第二输入端子和输出端子的延迟电路;输入检测电路检测输入信号的偏移;以及响应于偏移产生第一脉冲信号，输入检测电路连接到第一输入端子，以及用于产生控制信号的控制电路，每个控制信号分别响应于同步操作或异步操作产生。

7. 发明授权

US07076135B2 Optical module and manufacturing method therefor 有权
标题翻译：光模块及其制造方法
公开(公告)号：US07076135B2
公开(公告)日：2006-07-11
申请号：US10666482
申请日：2003-09-18
申请人： Koji Yamada , Tai Tsuchizawa , Shingo Uchiyama , Tetsufumi Shoji , Jyun-ichi Takahashi , Toshifumi Watanabe , Emi Tamechika , Hirofumi Morita
发明人： Koji Yamada , Tai Tsuchizawa , Shingo Uchiyama , Tetsufumi Shoji , Jyun-ichi Takahashi , Toshifumi Watanabe , Emi Tamechika , Hirofumi Morita
IPC分类号： G02B6/26 , G02B6/42 , G02B6/10
CPC分类号： G02B6/305 , G02B6/1228 , G02B2006/12176
摘要： An optical module includes an under cladding, a first core, a second core, and an over cladding. The under cladding has a flat shape as a whole. The first core has a quadrangular cross section and is placed on the under cladding. The second core is placed on a terminal end portion of the first core. The over cladding is placed in a region including the terminal end portion of the first core and the second core placed on the terminal end portion of the first core. The under cladding and the first core placed thereon constitute a first optical waveguide. The under cladding, the terminal end portion of the first core placed on the under cladding, the second core placed thereon, and the over cladding placed on and around the second core constitute a mode field size conversion portion. The under cladding, the second core placed on the under cladding, and the over cladding placed on and around the second core constitute a second optical waveguide. The first core is made of silicon. The first and second cores differ in cross-sectional shape. A manufacturing method for the optical module is also disclosed.
摘要翻译：光学模块包括下包层，第一芯，第二芯和外包层。下包层整体呈扁平形状。第一芯具有四边形横截面并且放置在下包层上。第二芯放置在第一芯的末端部分上。上包层放置在包括第一芯的末端部分和放置在第一芯的终端部分上的第二芯的区域中。下敷层和放置在其上的第一芯构成第一光波导。下包层，第一芯的终端部分放置在下包层上，第二芯放置在其上，并且放置在第二芯上和周围的上包层构成模场尺寸转换部分。放置在下包层上的下包层，第二芯和放置在第二芯上并围绕第二芯的外包层构成第二光波导。第一个核心由硅制成。第一和第二芯的横截面形状不同。还公开了一种用于光学模块的制造方法。

8. 发明授权

US06795496B1 Jitter measuring device and method 有权
标题翻译：抖动测量装置及方法
公开(公告)号：US06795496B1
公开(公告)日：2004-09-21
申请号：US09647908
申请日：2000-10-05
申请人： Mani Soma , Takahiro Yamaguchi , Masahiro Ishida , Yasuo Furukawa , Toshifumi Watanabe
发明人： Mani Soma , Takahiro Yamaguchi , Masahiro Ishida , Yasuo Furukawa , Toshifumi Watanabe
IPC分类号： H04B346
CPC分类号： G01R29/26
摘要： A signal under measurement is transformed into a complex analytic signal using a Hilbert transformer and an instantaneous phase of this analytic signal is estimated. A linear phase is subtracted from the instantaneous phase to obtain a phase noise waveform. The phase noise waveform is sampled in the proximity of a zero crossing point of a real part of the analytic signal. A differential waveform of the sample phase noise waveform is calculated to obtain a differential phase noise waveform. An RMS jitter is obtained from the phase noise waveform, and a peak-to-peak jitter is obtained from the phase noise waveform.
摘要翻译：使用希尔伯特变换器将测量信号转换为复杂的分析信号，并估计该分析信号的瞬时相位。从瞬时相位减去线性相位以获得相位噪声波形。相位噪声波形在分析信号的实部的零交叉点附近被采样。计算采样相位噪声波形的差分波形以获得差分相位噪声波形。从相位噪声波形获得RMS抖动，从相位噪声波形获得峰 - 峰抖动。

9. 发明授权

US6021288A Image forming apparatus 有权
标题翻译：图像形成装置
公开(公告)号：US6021288A
公开(公告)日：2000-02-01
申请号：US157495
申请日：1998-09-21
申请人： Yukihiko Okuno , Masaki Tanaka , Toshifumi Watanabe
发明人： Yukihiko Okuno , Masaki Tanaka , Toshifumi Watanabe
IPC分类号： B41J29/393 , G03G15/00 , G03G15/08
CPC分类号： G03G15/5041 , B41J29/393 , G03G15/5037 , G03G2215/00042
摘要： A digital copying machine develops an electrostatic latent image formed on a photosensitive drum with toner, and transfers the developed image onto a sheet. In forming images on the photosensitive drum successively, three types of test patterns are formed in order in intro-image areas between image forming areas, and AIDC is made. The first test pattern is a low-density pattern, the second test pattern is an intermediate-density pattern, and the third test pattern is a high-density pattern.
摘要翻译：数字复印机利用调色剂显影形成在感光鼓上的静电潜像，并将显影的图像转印到片材上。在感光鼓上依次形成图像时，在图像形成区域之间的内部图像区域中依次形成三种类型的测试图案，并且制作AIDC。第一测试图案是低密度图案，第二测试图案是中密度图案，第三测试图案是高密度图案。

10. 发明授权

US5925731A Endothelin antagonist peptides 失效
标题翻译：内皮素拮抗剂肽
公开(公告)号：US5925731A
公开(公告)日：1999-07-20
申请号：US732289
申请日：1996-10-28
申请人： Chieko Kitada , Taiji Asami , Tetsuya Ohtaki , Toshifumi Watanabe
发明人： Chieko Kitada , Taiji Asami , Tetsuya Ohtaki , Toshifumi Watanabe
IPC分类号： A61K38/00 , C07K5/02 , C07K5/103 , C07K14/575 , A61K38/07
CPC分类号： C07K14/57536 , C07K5/0202 , C07K5/101 , A61K38/00
摘要： The peptide derivatives having endothelin receptor-antagonistic action or a salt thereof and medicinal compositions containing them are provided.Since peptide derivatives or a salt thereof of this invention exhibit remarkable endothelin receptor-antagonistic action with low toxicity, they are effective as medicines for prophylaxis and therapy of, for example, cardio- or cerebro-circulatory diseases hepatic diseases and/or renal diseases.
摘要翻译： PCT No.PCT / JP96 / 02778 371日期1996年10月28日第 102（e）1996年10月28日PCT PCT 1996年9月26日PCT公布。公开号WO97 / 11961 日期1997年3月3日提供具有内皮素受体拮抗作用的肽衍生物或其盐和含有它们的药物组合物。由于本发明的肽衍生物或其盐表现出显着的低毒性的内皮素受体拮抗作用，因此它们作为预防和治疗例如心脏或脑循环疾病肝脏疾病和/或肾脏疾病的药物是有效的。

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