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    • 1. 发明申请
    • Inertia sensor unit
    • 惯性传感器单元
    • US20050183501A1
    • 2005-08-25
    • US10978785
    • 2004-10-15
    • Kazutaka SaitoAkira NakamutaIchiro UenoFumiki SatoSatoshi Hiyama
    • Kazutaka SaitoAkira NakamutaIchiro UenoFumiki SatoSatoshi Hiyama
    • G01C21/16G01P15/00G01P21/00G01P21/02
    • G01P21/00G01C21/16
    • An inertia sensor unit having a detecting element, a signal processor being constituted as an element separate from the detecting element, for at least amplifying signals output from the detecting element, and an inertia sensor mounted to a detection object for detecting acceleration or angular velocity of the detection object as an inertial force of the detection object to output electrical signals changing according to the inertial force, includes: a first temperature detecting means for detecting the temperature of the signal processor, a second temperature detecting means for detecting the temperature of the detecting element directly or indirectly, and a correcting means for correcting the signals output from the inertia sensor based on the result detected by the first temperature detecting means and the second temperature detecting means.
    • 惯性传感器单元,具有检测元件,信号处理器构成为与检测元件分离的元件,用于至少放大从检测元件输出的信号;以及惯性传感器,安装在检测对象上,用于检测加速度或角速度 作为检测对象的惯性力的检测对象输出根据惯性力而变化的电信号,包括:检测信号处理器的温度的第一温度检测单元,检测检测对象的温度的第二温度检测单元 以及校正装置,用于基于由第一温度检测装置和第二温度检测装置检测到的结果来校正从惯性传感器输出的信号。
    • 2. 发明授权
    • Inertia sensor unit
    • 惯性传感器单元
    • US07155974B2
    • 2007-01-02
    • US10978785
    • 2004-10-15
    • Kazutaka SaitoAkira NakamutaIchiro UenoFumiki SatoSatoshi Hiyama
    • Kazutaka SaitoAkira NakamutaIchiro UenoFumiki SatoSatoshi Hiyama
    • G01P3/00G01P21/00G01P15/00
    • G01P21/00G01C21/16
    • An inertia sensor unit having a detecting element, a signal processor being constituted as an element separate from the detecting element, for at least amplifying signals output from the detecting element, and an inertia sensor mounted to a detection object for detecting acceleration or angular velocity of the detection object as an inertial force of the detection object to output electrical signals changing according to the inertial force, includes: a first temperature detecting element for detecting the temperature of the signal processor, a second temperature detecting element for detecting the temperature of the detecting element directly or indirectly, and a correcting processor for correcting the signals output from the inertia sensor based on the result detected by the first temperature detecting element and the second temperature detecting element.
    • 惯性传感器单元,具有检测元件,信号处理器构成为与检测元件分离的元件,用于至少放大从检测元件输出的信号;以及惯性传感器,安装在检测对象上,用于检测加速度或角速度 作为检测对象的惯性力的检测对象输出根据惯性力而变化的电信号,包括:用于检测信号处理器的温度的第一温度检测元件,用于检测检测到的温度的第二温度检测元件 以及校正处理器,用于基于由第一温度检测元件和第二温度检测元件检测到的结果来校正从惯性传感器输出的信号。
    • 8. 发明授权
    • Multiplying circuit and microcomputer including the same
    • 乘法电路和微机包括相同
    • US5483477A
    • 1996-01-09
    • US205457
    • 1994-03-04
    • Fumiki SatoKouichi Fujita
    • Fumiki SatoKouichi Fujita
    • G06F7/49G06F7/48G06F7/52G06F7/533G06F7/00G06F15/00
    • G06F7/5338G06F7/4824
    • A multiplying circuit wherein an adder 7 outputs a value "0" in which both of a positive part and a negative part of a number with a redundant code are "1", and at a last cycle of the multiplication cycles, the finish detecting circuit 13 detects finishing of multiplication cycles by detecting that "1" exists in a portion storing a positive part of a number with a redundant code of the third bit from the lowest bit of the second latch 8 and in a portion storing a negative part of the same at the same time. In such a construction, a counter circuit for counting multiplication cycles according to the Booth algorithm utilizing a number with a redundant code can be omitted. Accordingly, the number of transistors is reduced and the circuit configuration becomes simple.
    • 乘法电路,其中加法器7输出其中具有冗余代码的数字的正部分和负部分都为“1”的值“0”,并且在乘法周期的最后一个周期,完成检测电路 13检测乘法周期的完成,通过检测在存储来自第二锁存器8的最低位的第三位的冗余代码的数字的正部分中存储的部分中存在“1”,并且存储负 同一时间。 在这种结构中,可以省略利用具有冗余码的数量的根据布斯算法进行乘法周期计数的计数器电路。 因此,晶体管的数量减少,电路结构变得简单。
    • 10. 发明授权
    • Buffer circuit which transfers data held in a first latch circuit to a
second latch circuit
    • 将保持在第一锁存电路中的数据传送到第二锁存电路的缓冲电路
    • US5926037A
    • 1999-07-20
    • US890619
    • 1997-07-09
    • Fumiki SatoKouichi Fujita
    • Fumiki SatoKouichi Fujita
    • G11C11/417G11C19/00H03K3/037H03K3/356H03K19/0175G11C7/00H03K19/094
    • H03K3/356191
    • A buffer circuit which can solve a problem of a conventional buffer circuit in that high speed data transfer is hindered because of parasitic capacitance of signal lines, which has an affect on the discharge time of inverters in a latch circuit of the buffer circuit, when the buffer circuit changes its state from a first term (non-transfer mode) to a second term (transfer mode). The buffer circuit solves this problem by pouring a current, which flows thereinto from a first signal line, into ground through a first PMOS transistor, a first NMOS transistor and a third NMOS transistor, and by pouring a current, which flows thereinto from a second signal line, into the ground through a second PMOS transistor, a second NMOS transistor and the third NMOS transistor.
    • 由于在对缓冲电路的锁存电路中的反相器的放电时间产生影响的信号线的寄生电容的情况下,可以解决在该高速数据传输中解决现有的缓冲电路的问题的缓冲电路, 缓冲电路将其状态从第一项(非转移模式)改变为第二项(传输模式)。 缓冲电路通过将从第一信号线流入的电流通过第一PMOS晶体管,第一NMOS晶体管和第三NMOS晶体管注入接地来解决这个问题,并且通过从第二PMOS晶体管,第一NMOS晶体管和第三NMOS晶体管中流入的电流 信号线通过第二PMOS晶体管,第二NMOS晶体管和第三NMOS晶体管插入地。