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1. 发明申请

US20090140409A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090140409A1
公开(公告)日：2009-06-04
申请号：US12327649
申请日：2008-12-03
申请人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Dai Sasaki
发明人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Dai Sasaki
IPC分类号： H01L23/48
CPC分类号： H01L23/3135 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/03 , H01L2224/06135 , H01L2224/06136 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48011 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/484 , H01L2224/48599 , H01L2224/48699 , H01L2224/49 , H01L2224/73215 , H01L2224/73265 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/00012 , H01L2224/32225 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor device includes a substrate having bumps on the backside thereof, a first semiconductor chip mounted on the surface of the substrate, a second semiconductor chip mounted on the first semiconductor chip above the surface of the substrate, a first bonding wire having a length L1 for connecting the first semiconductor chip to the substrate, a second bonding wire having a length L2 (where L2>L1) for connecting the second semiconductor chip to the substrate, a first resin seal having a dielectric constant ε1 for sealing the first bonding wire, and a second resin seal having a dielectric constant ε2 (where ε2
摘要翻译：半导体器件包括其背面具有凸块的衬底，安装在衬底表面上的第一半导体芯片，安装在衬底表面上的第一半导体芯片上的第二半导体芯片，具有长度L1 为了将第一半导体芯片连接到基板，具有用于将第二半导体芯片连接到基板的长度L2（其中L2> L1）的第二接合线，具有用于密封第一接合线的介电常数ε1的第一树脂密封件，以及具有用于密封第二接合线的介电常数ε2（其中ε2 <ε1）的第二树脂密封件。长度L1和L2之间的关系以及介电常数ε1和ε2由ε1= epsilon2（L2 / L1）2的等式定义。

2. 发明授权

US08063476B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08063476B2
公开(公告)日：2011-11-22
申请号：US12327649
申请日：2008-12-03
申请人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Dai Sasaki
发明人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Dai Sasaki
IPC分类号： H01L23/02
CPC分类号： H01L23/3135 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/03 , H01L2224/06135 , H01L2224/06136 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48011 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/484 , H01L2224/48599 , H01L2224/48699 , H01L2224/49 , H01L2224/73215 , H01L2224/73265 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/00012 , H01L2224/32225 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor device includes a substrate having bumps on the backside thereof, a first semiconductor chip mounted on the surface of the substrate, a second semiconductor chip mounted on the first semiconductor chip above the surface of the substrate, a first bonding wire having a length L1 for connecting the first semiconductor chip to the substrate, a second bonding wire having a length L2 (where L2>L1) for connecting the second semiconductor chip to the substrate, a first resin seal having a dielectric constant ∈1 for sealing the first bonding wire, and a second resin seal having a dielectric constant ∈2 (where ∈2
摘要翻译：半导体器件包括其背面具有凸块的衬底，安装在衬底表面上的第一半导体芯片，安装在衬底表面上的第一半导体芯片上的第二半导体芯片，具有长度L1 用于将第一半导体芯片连接到基板的第二接合线，具有用于将第二半导体芯片连接到基板的长度L2（其中L2> L1）的第二接合线，具有介电常数ε1的第一树脂密封件，用于密封第一接合线以及用于密封第二接合线的介电常数ε2（其中∈2<∈1）的第二树脂密封。长度L1和L2之间的关系以及介电常数∈1和∈2由∈1=∈2（L2 / L1）2的方程定义。

3. 发明申请

US20070164435A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070164435A1
公开(公告)日：2007-07-19
申请号：US11613914
申请日：2006-12-20
申请人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Fumiyuki Osanai
发明人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Fumiyuki Osanai
IPC分类号： H01L23/52
CPC分类号： H01L23/66 , H01L23/49822 , H01L2224/48227 , H01L2224/49175 , H01L2924/19051 , H01L2924/3011 , H01L2924/3025 , H05K1/0216 , H05K1/024 , H05K3/4688 , H05K2201/09309 , H01L2924/00
摘要： To reduce noise between a power supply wiring and ground wiring especially in a small, high-density semiconductor device for high-speed operation. A semiconductor device having a second dielectric layer 5 made of dielectric material of which the dielectric loss tan 6 is at least 0.2 and interposed between a power supply wiring layer 6 electrically connected to a semiconductor chip and a ground wiring layer 4, so composed that a dielectric loss generated in the second dielectric layer 5 acts as a low pass filter of the power supply wiring layer 6, and having a first dielectric layer 3 made of dielectric material whose dielectric loss is less than the dielectric loss tan 6 of the second dielectric layer 5 and interposed between a signal wiring layer 2 electrically connected to the semiconductor chip and the ground wiring layer 4.
摘要翻译：为了降低电源布线和接地布线之间的噪音，特别是在高速运行的小型，高密度半导体器件中。一种半导体器件，具有由绝缘材料制成的介电损耗tanδ为0.2以上且介于与半导体芯片电连接的电源布线层6和接地布线层4之间的第二介质层5，在第二电介质层5中产生的介电损耗用作电源布线层6的低通滤波器，并且具有由介电损耗小于第二介电层的介电损耗tanδ的电介质材料制成的第一电介质层3 插入在与半导体芯片电连接的信号布线层2和接地布线层4之间。

4. 发明授权

US07944026B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07944026B2
公开(公告)日：2011-05-17
申请号：US11962142
申请日：2007-12-21
申请人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Haruo Akahoshi
发明人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Haruo Akahoshi
IPC分类号： H01L29/40
CPC分类号： H01L23/66 , H01L23/647 , H01L2223/6638 , H01L2924/0002 , H01L2924/19051 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is mounted on a package substrate which has a power supply line and a signal line formed of a normal or predetermined resistance material layer on a dielectric layer. A resistance material layer has a high resistance as compared with the normal resistance material layer and is additionally provided on the surface of the normal resistance material layer of the peripheral face of the signal line closest to the power supply line.
摘要翻译：半导体器件安装在封装衬底上，该封装衬底具有电源线和由介电层上的正常或预定电阻材料层形成的信号线。电阻材料层与普通电阻材料层相比具有高电阻，并且附加地设置在最靠近电源线的信号线的外围面的正常电阻材料层的表面上。

5. 发明授权

US07816768B2 Semiconductor device including ground and power-supply planes and a dielectric layer between the ground and power-supply planes 有权
标题翻译：包括接地和供电平面的半导体器件以及接地和电源平面之间的介电层
公开(公告)号：US07816768B2
公开(公告)日：2010-10-19
申请号：US12007758
申请日：2008-01-15
申请人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa
发明人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa
IPC分类号： H01L23/58 , H01L23/62
CPC分类号： H01L23/50 , H01L24/32 , H01L24/50 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/04953 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011
摘要： A high dielectric loss tangent layer is provided in a dielectric layer between a power-supply plane and a ground plane. The high dielectric loss tangent layer is arranged such that its edge is located between the edge of the power-supply plane and the edge of the ground plane. The edge of the high dielectric loss tangent layer is preferably separated by a predetermined distance or more from the edge of the power-supply plane or the edge of the ground plane which is located on the inner side.
摘要翻译：在电源平面和接地平面之间的电介质层中设置高介电损耗切线层。高介电损耗切线层被布置为使得其边缘位于电源平面的边缘和接地平面的边缘之间。高介电损耗切线层的边缘优选从电源平面的边缘或位于内侧的接地平面的边缘分开预定距离或更大的距离。

6. 发明申请

US20100095257A1 ELECTROMAGNETIC FIELD ANALYSIS OF SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CHIP MOUNTED THEREON 审中-公开
标题翻译：具有半导体芯片安装的半导体封装的电磁场分析
公开(公告)号：US20100095257A1
公开(公告)日：2010-04-15
申请号：US12574980
申请日：2009-10-07
申请人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa
发明人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： An electromagnetic field analysis of a semiconductor package with a semiconductor chip mounted thereon can be performed simply with a high accuracy. First modeling and second modeling of the semiconductor package with the semiconductor chip mounted thereon are carried out, thereby performing first and second electromagnetic field analyses. Results of the first and second electromagnetic field analyses are synthesized to determine electrical characteristics of the semiconductor package. Specifically, an inductance analysis is performed with the entire semiconductor chip regarded as a dielectric, thereby determining an inductance component of an equivalent circuit. A capacitance analysis is performed with the semiconductor chip regarded as a dielectric having a metal thin film on its surface, thereby determining a capacitance component of an equivalent circuit. Results of the inductance analysis and the capacitance analysis are synthesized to determine an equivalent circuit.
摘要翻译：可以简单地以高精度进行安装有半导体芯片的半导体封装的电磁场分析。对其上安装有半导体芯片的半导体封装的第一建模和第二建模进行，从而进行第一和第二电磁场分析。合成第一和第二电磁场分析的结果以确定半导体封装的电特性。具体地说，以整个半导体芯片作为电介质进行电感分析，从而确定等效电路的电感分量。在半导体芯片被认为是其表面具有金属薄膜的电介质的情况下进行电容分析，从而确定等效电路的电容分量。电感分析和电容分析的结果被合成以确定等效电路。

7. 发明申请

US20080164585A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080164585A1
公开(公告)日：2008-07-10
申请号：US11962142
申请日：2007-12-21
申请人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Haruo Akahoshi
发明人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Haruo Akahoshi
IPC分类号： H01L23/488
CPC分类号： H01L23/66 , H01L23/647 , H01L2223/6638 , H01L2924/0002 , H01L2924/19051 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is mounted on a package substrate which has a power supply line and a signal line formed of a normal or predetermined resistance material layer on a dielectric layer. A resistance material layer has a high resistance as compared with the normal resistance material layer and is additionally provided on the surface of the normal resistance material layer of the peripheral face of the signal line closest to the power supply line.
摘要翻译：半导体器件安装在封装衬底上，该封装衬底具有电源线和由介电层上的正常或预定电阻材料层形成的信号线。电阻材料层与普通电阻材料层相比具有高电阻，并且附加地设置在最靠近电源线的信号线的外围面的正常电阻材料层的表面上。

8. 发明申请

US20080173987A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080173987A1
公开(公告)日：2008-07-24
申请号：US12007758
申请日：2008-01-15
申请人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa
发明人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L24/32 , H01L24/50 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/04953 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011
摘要： A high dielectric loss tangent layer is provided in a dielectric layer between a power-supply plane and a ground plane. The high dielectric loss tangent layer is arranged such that its edge is located between the edge of the power-supply plane and the edge of the ground plane. The edge of the high dielectric loss tangent layer is preferably separated by a predetermined distance or more from the edge of the power-supply plane or the edge of the ground plane which is located on the inner side.
摘要翻译：在电源平面和接地平面之间的电介质层中设置高介电损耗切线层。高介电损耗切线层被布置为使得其边缘位于电源平面的边缘和接地平面的边缘之间。高介电损耗切线层的边缘优选从电源平面的边缘或位于内侧的接地平面的边缘分开预定距离或更大的距离。

9. 发明申请

US20120146242A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120146242A1
公开(公告)日：2012-06-14
申请号：US13323246
申请日：2011-12-12
申请人： Hiroyuki Fujishima , Dai Sasaki , Satoshi Isa , Mitsuaki Katagiri
发明人： Hiroyuki Fujishima , Dai Sasaki , Satoshi Isa , Mitsuaki Katagiri
IPC分类号： H01L23/498
CPC分类号： H01L21/563 , H01L21/561 , H01L23/3128 , H01L23/3185 , H01L23/481 , H01L23/49816 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/83192 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/01029 , H01L2924/15311 , H01L2924/181 , H01L2224/81 , H01L2924/00 , H01L2924/3512 , H01L2924/00012
摘要： A semiconductor device includes a wiring board, a stack of semiconductor chips, and a first sealing member. The wiring board has a first surface. The wiring board includes a first insulating layer formed over the first surface. The first insulating layer has a first opening. The stack of semiconductor chips is mounted over the first surface of the wiring board. The stack of semiconductor chips includes a first semiconductor chip. The first semiconductor chip is closer to the wiring board than the other semiconductor chips. The first sealing member seals at least the first semiconductor chip. The first sealing member includes a protruding portion. The first opening of the insulating layer faces toward the protruding portion of the first sealing member.
摘要翻译：半导体器件包括布线板，半导体芯片堆叠和第一密封构件。布线板具有第一表面。布线板包括形成在第一表面上的第一绝缘层。第一绝缘层具有第一开口。半导体芯片的堆叠被安装在布线板的第一表面上。半导体芯片堆叠包括第一半导体芯片。第一半导体芯片比其他半导体芯片更接近布线板。第一密封构件至少密封第一半导体芯片。第一密封构件包括突出部。绝缘层的第一开口朝向第一密封构件的突出部分。

10. 发明授权

US07777350B2 Semiconductor stack package having wiring extension part which has hole for wiring 有权
标题翻译：半导体堆叠封装，具有布线延伸部分，其具有用于布线的孔
公开(公告)号：US07777350B2
公开(公告)日：2010-08-17
申请号：US12219839
申请日：2008-07-29
申请人： Dai Sasaki , Mitsuaki Katagiri , Satoshi Isa
发明人： Dai Sasaki , Mitsuaki Katagiri , Satoshi Isa
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40 , H01L23/02 , H01L27/146 , H01L27/148
CPC分类号： H01L25/0657 , H01L23/3128 , H01L24/06 , H01L24/45 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/32145 , H01L2224/45015 , H01L2224/45144 , H01L2224/48227 , H01L2224/4824 , H01L2224/4911 , H01L2224/85399 , H01L2225/0651 , H01L2225/06517 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor stack package includes a first printed wiring board; a plurality of semiconductor chips stacked on the first printed wiring board, wherein among the semiconductor chips, the uppermost semiconductor chip has an electrode pad for providing power supply, a ground pad for providing grounding, and a signal pad for signal transmission in a center area on the upper surface of the chip; connection lands formed on the first printed wiring board on the outside of the stacked semiconductor chips; a wiring extension part which is formed on the uppermost semiconductor chip, and has wiring circuits extending from the center to the periphery thereof, wherein at least one of the electrode pad and the ground pad is electrically connected to one end of one of the wiring circuits; and a wire for connecting the other end of the relevant wiring circuit of the wiring extension part and one of the connection lands on the first printed wiring board.
摘要翻译：半导体堆叠封装包括第一印刷线路板; 堆叠在第一印刷线路板上的多个半导体芯片，其中在半导体芯片中，最上半导体芯片具有用于提供电源的电极焊盘，用于提供接地的接地焊盘和用于在中心区域中进行信号传输的信号焊盘在芯片的上表面; 在叠层半导体芯片的外侧的第一印刷布线板上形成的连接焊盘; 布线延伸部，形成在最上半导体芯片上，并且具有从中心延伸到其周边的布线电路，其中电极焊盘和接地焊盘中的至少一个电连接到一个布线电路的一端 ; 以及用于连接布线延伸部分的相关布线电路的另一端和第一印刷布线板上的一个连接焊盘的导线。

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