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1. 发明申请

US20070164435A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070164435A1
公开(公告)日：2007-07-19
申请号：US11613914
申请日：2006-12-20
申请人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Fumiyuki Osanai
发明人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Fumiyuki Osanai
IPC分类号： H01L23/52
CPC分类号： H01L23/66 , H01L23/49822 , H01L2224/48227 , H01L2224/49175 , H01L2924/19051 , H01L2924/3011 , H01L2924/3025 , H05K1/0216 , H05K1/024 , H05K3/4688 , H05K2201/09309 , H01L2924/00
摘要： To reduce noise between a power supply wiring and ground wiring especially in a small, high-density semiconductor device for high-speed operation. A semiconductor device having a second dielectric layer 5 made of dielectric material of which the dielectric loss tan 6 is at least 0.2 and interposed between a power supply wiring layer 6 electrically connected to a semiconductor chip and a ground wiring layer 4, so composed that a dielectric loss generated in the second dielectric layer 5 acts as a low pass filter of the power supply wiring layer 6, and having a first dielectric layer 3 made of dielectric material whose dielectric loss is less than the dielectric loss tan 6 of the second dielectric layer 5 and interposed between a signal wiring layer 2 electrically connected to the semiconductor chip and the ground wiring layer 4.
摘要翻译：为了降低电源布线和接地布线之间的噪音，特别是在高速运行的小型，高密度半导体器件中。一种半导体器件，具有由绝缘材料制成的介电损耗tanδ为0.2以上且介于与半导体芯片电连接的电源布线层6和接地布线层4之间的第二介质层5，在第二电介质层5中产生的介电损耗用作电源布线层6的低通滤波器，并且具有由介电损耗小于第二介电层的介电损耗tanδ的电介质材料制成的第一电介质层3 插入在与半导体芯片电连接的信号布线层2和接地布线层4之间。

2. 发明申请

US20060249842A1 Semiconductor device 有权
公开(公告)号：US20060249842A1
公开(公告)日：2006-11-09
申请号：US11391449
申请日：2006-03-29
申请人： Satoshi Isa , Mitsuaki Katagiri , Fumiyuki Osanai
发明人： Satoshi Isa , Mitsuaki Katagiri , Fumiyuki Osanai
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L23/3114 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.

3. 发明授权

US07569428B2 Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same 有权
标题翻译：制造半导体器件的方法，半导体器件及包括该器件的器件
公开(公告)号：US07569428B2
公开(公告)日：2009-08-04
申请号：US11525952
申请日：2006-09-25
申请人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
发明人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H01L21/82 , H01L23/52
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.
摘要翻译：公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据预定的布局。多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。

4. 发明申请

US20070069362A1 Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same 有权
标题翻译：制造半导体器件的方法，半导体器件及包括该器件的器件
公开(公告)号：US20070069362A1
公开(公告)日：2007-03-29
申请号：US11525952
申请日：2006-09-25
申请人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
发明人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.
摘要翻译：公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据预定的布局。多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。

5. 发明授权

US07538431B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07538431B2
公开(公告)日：2009-05-26
申请号：US12126681
申请日：2008-05-23
申请人： Satoshi Isa , Mitsuaki Katagiri , Fumiyuki Osanai
发明人： Satoshi Isa , Mitsuaki Katagiri , Fumiyuki Osanai
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L23/3114 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.
摘要翻译：公开了一种半导体器件，其包括数据族焊盘布局，其中努力设计电源引线和接地引线的布局，以将焊盘和焊球焊盘之间的引线的长度优先于最小化有效电感的半导体芯片。焊盘布局排列成两行，并且焊盘布局的一个单位被配置为使得数据电源和接地彼此相邻或者在数据电源和地之间插入一个数据。这样的配置减少数据电源之间的互感，并增加数据电源和地之间的互感，从而导致数据电源与地之间的有效电感的降低，从而导致功率和接地噪声的最小化。

6. 发明授权

US07847377B2 Semiconductor device including semiconductor chip with two pad rows 有权
标题翻译：半导体器件包括具有两个焊盘行的半导体芯片
公开(公告)号：US07847377B2
公开(公告)日：2010-12-07
申请号：US11528688
申请日：2006-09-28
申请人： Fumiyuki Osanai , Mitsuaki Katagiri , Satoshi Isa
发明人： Fumiyuki Osanai , Mitsuaki Katagiri , Satoshi Isa
IPC分类号： H01L27/07
CPC分类号： H01L23/50 , H01L23/49838 , H01L23/4985 , H01L24/06 , H01L2224/05554
摘要： A semiconductor device includes a semiconductor chip having at a center area thereof first and second pad rows which include a plurality of first pads and a plurality of second pads, respectively. A package substrate is bonded to the semiconductor chip. The package substrate includes a substrate opening corresponding to a region including the first and second pad rows, first and second wiring positioned at opposite sides of the substrate opening, respectively, and a ball land disposed in the first wiring area. A bridge section is provided over the substrate opening to mutually connect the first and second wiring areas. The ball land is electrically connected to at least one of the second pads through the bridge section by a lead.
摘要翻译：半导体器件包括半导体芯片，其半导体芯片在其中心区域具有分别包括多个第一焊盘和多个第二焊盘的第一焊盘行和第二焊盘行。封装基板结合到半导体芯片。封装基板包括对应于包括第一和第二焊盘列的区域的基板开口，分别位于基板开口的相对侧的第一和第二布线以及设置在第一布线区域中的球形区域。桥接部分设置在基板开口上方以相互连接第一和第二布线区域。球面通过导线通过桥接部分电连接到第二焊盘中的至少一个。

7. 发明授权

US07391113B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07391113B2
公开(公告)日：2008-06-24
申请号：US11391449
申请日：2006-03-29
申请人： Satoshi Isa , Mitsuaki Katagiri , Fumiyuki Osanai
发明人： Satoshi Isa , Mitsuaki Katagiri , Fumiyuki Osanai
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L23/3114 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.
摘要翻译：公开了一种半导体器件，其包括数据族焊盘布局，其中努力设计电源引线和接地引线的布局，以将焊盘和焊球焊盘之间的引线的长度优先于最小化有效电感的半导体芯片。焊盘布局排列成两行，并且焊盘布局的一个单位被配置为使得数据电源和接地彼此相邻或者在数据电源和地之间插入一个数据。这样的配置减少数据电源之间的互感，并增加数据电源和地之间的互感，从而导致数据电源与地之间的有效电感的降低，从而导致功率和接地噪声的最小化。

8. 发明申请

US20070075440A1 Semiconductor device including semiconductor chip with two pad rows 有权
标题翻译：半导体器件包括具有两个焊盘行的半导体芯片
公开(公告)号：US20070075440A1
公开(公告)日：2007-04-05
申请号：US11528688
申请日：2006-09-28
申请人： Fumiyuki Osanai , Mitsuaki Katagiri , Satoshi Isa
发明人： Fumiyuki Osanai , Mitsuaki Katagiri , Satoshi Isa
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L23/49838 , H01L23/4985 , H01L24/06 , H01L2224/05554
摘要： A semiconductor device includes a semiconductor chip having at a center area thereof first and second pad rows which include a plurality of first pads and a plurality of second pads, respectively. A package substrate is bonded to the semiconductor chip. The package substrate includes a substrate opening corresponding to a region including the first and second pad rows, first and second wiring positioned at opposite sides of the substrate opening, respectively, and a ball land disposed in the first wiring area. A bridge section is provided over the substrate opening to mutually connect the first and second wiring areas. The ball land is electrically connected to at least one of the second pads through the bridge section by a lead.
摘要翻译：半导体器件包括半导体芯片，其半导体芯片在其中心区域具有分别包括多个第一焊盘和多个第二焊盘的第一焊盘行和第二焊盘行。封装基板结合到半导体芯片。封装基板包括对应于包括第一和第二焊盘列的区域的基板开口，分别位于基板开口的相对侧的第一和第二布线以及设置在第一布线区域中的球形区域。桥接部分设置在基板开口上方以相互连接第一和第二布线区域。球面通过导线通过桥接部分电连接到第二焊盘中的至少一个。

9. 发明授权

US07714424B2 Stacked-type semiconductor package 有权
标题翻译：堆叠型半导体封装
公开(公告)号：US07714424B2
公开(公告)日：2010-05-11
申请号：US12081264
申请日：2008-04-14
申请人： Mitsuaki Katagiri , Atsushi Hiraishi , Fumiyuki Osanai
发明人： Mitsuaki Katagiri , Atsushi Hiraishi , Fumiyuki Osanai
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/3128 , H01L25/105 , H01L2224/50 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311
摘要： Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path.
摘要翻译：与第一半导体芯片的第一信号传输路径中的第一路径部分的对应部分是互连部件和第二路径部分，到第二半导体芯片的第二信号传输路径，并且不形成在第一条带上。允许第二信号传输路径的电长度独立于第一带被调整，使得第二信号传输路径的电长度可以容易地等于或基本等于第一信号传输路径的电长度。

10. 发明授权

US08362614B2 Fine pitch grid array type semiconductor device 有权
标题翻译：细间距阵列型半导体器件
公开(公告)号：US08362614B2
公开(公告)日：2013-01-29
申请号：US11247215
申请日：2005-10-12
申请人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
发明人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/50 , H01L23/49838 , H01L2224/4824 , H01L2924/13091 , H01L2924/15173 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.
摘要翻译：半导体器件具有其中布置有多个半导体部件和多个焊盘的半导体芯片，布置在栅格中的多个外部连接触点，以及用于电连接焊盘和外部连接触点的多条引线。焊盘包括多个焊盘组，其包括连接到共同的多个半导体部件的一对电极焊盘和分别连接到连接到电极焊盘的半导体部件的多个信号焊盘。在每个焊盘组中，每个信号焊盘被布置成与电极焊盘之一相邻; 并且从每个信号焊盘延伸的每条焊丝沿着与每个信号焊盘相邻的电极焊盘延伸的焊丝延伸。

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