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1. 发明授权

US06522583B2 Nonvolatile semiconductor memory 有权
公开(公告)号：US06522583B2
公开(公告)日：2003-02-18
申请号：US09860613
申请日：2001-05-21
申请人： Kazushige Kanda , Hiroshi Nakamura , Koji Hosono , Tamio Ikehashi , Kenichi Imamiya
发明人： Kazushige Kanda , Hiroshi Nakamura , Koji Hosono , Tamio Ikehashi , Kenichi Imamiya
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0483
摘要： A drain-side select gate line is set to VSG1 (>VDD) capable of sufficiently transferring VDD (time t1). Since all word lines in the selected block are set to Vread, VDD is applied to the channels of all memory cells in the cell units. After this, the drain-side select gate line is set to VSG2, and a program potential Vpgm is applied to the selected word line (times t2 to t3). Since VSG2 is sufficiently low, all drain-side select gate transistors are kept off, and the channel potentials of memory cells in all cell units are boosted. After this, since the drain-side select gate line is set to VSG3, the channel of the selected memory cell is set to 0V (time t4).

2. 发明授权

US07633826B2 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used 有权
标题翻译：半导体器件，非易失性半导体存储器，包括多个半导体器件或非易失性半导体存储器的系统，包括半导体器件或非易失性半导体存储器的电卡，以及可以使用该电卡的电子器件
公开(公告)号：US07633826B2
公开(公告)日：2009-12-15
申请号：US11938756
申请日：2007-11-12
申请人： Kazushige Kanda , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi , Tamio Ikehashi
发明人： Kazushige Kanda , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi , Tamio Ikehashi
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C17/18
摘要： A semiconductor device of this invention includes a first circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, a second circuit for controlling the output from the first circuit by activation or deactivation, and an activation control circuit for activating or deactivating the second circuit in accordance with external input.
摘要翻译：本发明的半导体器件包括用于根据电源电压的电平初始化预定电路的第一电路，用于通过激活或去激活来控制来自第一电路的输出的第二电路，以及用于激活或去激活的激活控制电路，根据外部输入禁用第二电路。

3. 发明授权

US07116603B2 Non-volatile semiconductor storage device performing ROM read operation upon power-on 有权
标题翻译：上电时执行ROM读取操作的非易失性半导体存储装置
公开(公告)号：US07116603B2
公开(公告)日：2006-10-03
申请号：US10648853
申请日：2003-08-26
申请人： Kazushige Kanda , Hiroshi Nakamura
发明人： Kazushige Kanda , Hiroshi Nakamura
IPC分类号： G11C7/00
CPC分类号： G11C16/20 , G11C16/30
摘要： A power-on reset circuit has a power-on level detecting circuit which detects a power voltage to output a power-on reset signal and a delay circuit which delays the power-on reset signal output by the power-on level detecting circuit. Two chip address specifying pads are connected to the delay circuit. Delay time in the delay time is controlled according to a chip address supplied to these two pads.
摘要翻译：上电复位电路具有检测电源电压以输出上电复位信号的上电电平检测电路和延迟由通电电平检测电路输出的上电复位信号的延迟电路。两个芯片地址指定焊盘连接到延迟电路。根据提供给这两个焊盘的芯片地址来控制延迟时间的延迟时间。

4. 发明授权

US07057947B2 SEMICONDUCTOR DEVICE, NONVOLATILE SEMICONDUCTOR MEMORY, SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR DEVICES OR NONVOLATILE SEMICONDUCTOR MEMORIES, ELECTRIC CARD INCLUDING SEMICONDUCTOR DEVICE OR NONVOLATILE SEMICONDUCTOR MEMORY, AND ELECTRIC DEVICE WITH WHICH THIS ELECTRIC CARD CAN BE USED 有权
标题翻译：半导体器件，非易失性半导体存储器，包括多个半导体器件或非易失性半导体存储器的系统，包括半导体器件或非易失性半导体存储器的电子卡，以及可以使用该电卡的电子器件
公开(公告)号：US07057947B2
公开(公告)日：2006-06-06
申请号：US10322785
申请日：2002-12-18
申请人： Kazushige Kanda , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi , Tamio Ikehashi
发明人： Kazushige Kanda , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi , Tamio Ikehashi
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C17/18
摘要： A semiconductor device of this invention includes a first circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, a second circuit for controlling the output from the first circuit by activation or deactivation, and an activation control circuit for activating or deactivating the second circuit in accordance with external input.
摘要翻译：本发明的半导体器件包括用于根据电源电压的电平初始化预定电路的第一电路，用于通过激活或去激活来控制来自第一电路的输出的第二电路，以及用于激活或去激活的激活控制电路，根据外部输入禁用第二电路。

5. 发明授权

US06870786B2 SEMICONDUCTOR DEVICE, NONVOLATILE SEMICONDUCTOR MEMORY, SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR DEVICES OR NONVOLATILE SEMICONDUCTOR MEMORIES, ELECTRIC CARD INCLUDING SEMICONDUCTOR DEVICE OR NONVOLATILE SEMICONDUCTOR MEMORY, AND ELECTRIC DEVICE WITH WHICH THIS ELECTRIC CARD CAN BE USED 有权
标题翻译：半导体器件，非易失性半导体存储器，包括多个半导体器件或非易失性半导体存储器的系统，包括半导体器件或非易失性半导体存储器的电子卡，以及可以使用该电卡的电子器件
公开(公告)号：US06870786B2
公开(公告)日：2005-03-22
申请号：US10322349
申请日：2002-12-18
申请人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
发明人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C16/06 , G11C7/10 , G11C7/20 , G11C16/00 , G11C16/20 , G11C16/30 , G11C29/04 , H03K17/22 , G11C7/00
CPC分类号： G11C7/1063 , G11C7/1051 , G11C7/20 , G11C16/20 , G11C16/30
摘要： A semiconductor device of this invention includes an initialization circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, and a status setting unit for setting the status of the semiconductor device to “busy” during a period in which the initialization circuit performs initialization.
摘要翻译：本发明的半导体器件包括：初始化电路，用于根据电源电压的电平初始化预定电路;以及状态设置单元，用于在初始化期间将半导体器件的状态设置为“忙” 电路执行初始化。

6. 发明授权

US06201434B1 Semiconductor integrated circuit device having an oscillation circuit using reference current source independent from influence of variation of power supply voltage and threshold voltage of transistor 失效
标题翻译：具有使用参考电流源的振荡电路的半导体集成电路器件，独立于晶体管的电源电压和阈值电压的变化的影响
公开(公告)号：US06201434B1
公开(公告)日：2001-03-13
申请号：US09061064
申请日：1998-04-16
申请人： Kazushige Kanda , Hiroshi Nakamura
发明人： Kazushige Kanda , Hiroshi Nakamura
IPC分类号： G05F302
CPC分类号： G05F3/247 , G05F3/262 , H03K3/0231
摘要： A semiconductor integrated circuit includes the reference current generating circuit free from both the influence of a power supply voltage and the influence of the variation of the threshold voltage of the transistors related to the generation of the reference current. In the reference current generating circuit, a P-channel MOS transistor (Qp1), a N-channel MOS transistor (Qn1), a resistor element (R1), and a N-channel MOS transistor (Qn2) are connected in series between the power supply voltage and the ground. The gate and the drain of the N-channel MOS transistor (Qn2) are connected by a short circuit to output the reference current Iref from a transistor (Qn6) through the resistor element. The integrated circuit is provided with a level shifter connected to the reference current generating circuit such that the threshold voltages of the N-channel transistors (Qn1, Qn2) are added to a reference voltage Vref by N-channel transistors (Qn3, Qn4) in the level shifter, and the resultant reference voltage Vref is applied to the gate of the N-channel transistors (Qn1).
摘要翻译：半导体集成电路包括不受电源电压的影响和与产生参考电流相关的晶体管的阈值电压的变化的影响的参考电流产生电路。在参考电流产生电路中，P沟道MOS晶体管（Qp1），N沟道MOS晶体管（Qn1），电阻元件（R1）和N沟道MOS晶体管（Qn2）串联连接电源电压和地。 N沟道MOS晶体管（Qn2）的栅极和漏极通过短路连接，通过电阻元件从晶体管（Qn6）输出参考电流Iref。集成电路设置有与基准电流产生电路连接的电平转换器，使得N沟道晶体管（Qn1，Qn2）的阈值电压通过N沟道晶体管（Qn3，Qn4）加到基准电压Vref 电平移位器，并将得到的参考电压Vref施加到N沟道晶体管（Qn1）的栅极。

7. 发明授权

US07123526B2 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used 有权
标题翻译：半导体器件，非易失性半导体存储器，包括多个半导体器件或非易失性半导体存储器的系统，包括半导体器件或非易失性半导体存储器的电卡，以及可以使用该电卡的电子器件
公开(公告)号：US07123526B2
公开(公告)日：2006-10-17
申请号：US11337999
申请日：2006-01-24
申请人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
发明人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C7/00
CPC分类号： G11C7/1063 , G11C7/1051 , G11C7/20 , G11C16/20 , G11C16/30
摘要： A semiconductor device of this invention includes an initialization circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, and a status setting unit for setting the status of the semiconductor device to “busy” during a period in which the initialization circuit performs initialization.
摘要翻译：本发明的半导体器件包括：初始化电路，用于根据电源电压的电平初始化预定电路;以及状态设置单元，用于在初始化期间将半导体器件的状态设置为“忙” 电路执行初始化。

8. 发明申请

US20060039225A1 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used 有权
公开(公告)号：US20060039225A1
公开(公告)日：2006-02-23
申请号：US11203393
申请日：2005-08-12
申请人： Kazushige Kanda , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi , Tamio Ikehashi
发明人： Kazushige Kanda , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi , Tamio Ikehashi
IPC分类号： G11C5/14
CPC分类号： G11C5/143 , G11C17/18
摘要： A semiconductor device of this invention includes a first circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, a second circuit for controlling the output from the first circuit by activation or deactivation, and an activation control circuit for activating or deactivating the second circuit in accordance with external input.

9. 发明授权

US07372761B2 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used 有权
标题翻译：半导体器件，非易失性半导体存储器，包括多个半导体器件或非易失性半导体存储器的系统，包括半导体器件或非易失性半导体存储器的电卡，以及可以使用该电卡的电子器件
公开(公告)号：US07372761B2
公开(公告)日：2008-05-13
申请号：US11521694
申请日：2006-09-15
申请人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
发明人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C7/00
CPC分类号： G11C7/1063 , G11C7/1051 , G11C7/20 , G11C16/20 , G11C16/30
摘要： The object is to avoid an erroneous operation during a term in which an initialization is performed when a command is input.After a power source is turned on, a low level of a power-on-reset signal PWONRSTn is output until it reaches a power-on detect level. It is inverted by an inverter IN11, and input to a NOR circuit NR 11 likewise commands 1 and 2, so that a status is set to a busy status. The busy status is kept during a term in which a initialization operation is performed until the power supply voltage reaches the power-on detect level. Further, the status is read out to the exterior by a status read out mode signal to notify a user. As a result, it prevents from being input a command by an erroneous operation of a user during the initialization operation term.
摘要翻译：目的是避免在输入命令时执行初始化的术语期间的错误操作。电源接通后，输出低电平上电复位信号PWONRSTn，直到达到上电检测电平。它由反相器IN11反相，并且输入到NOR电路NR11同样命令1和2，使得状态被设置为忙状态。在执行初始化操作的期间内保持忙碌状态，直到电源电压达到上电检测电平。此外，通过状态读出模式信号将状态读出到外部，以通知用户。结果，它防止了在初始化操作期间通过用户的错误操作来输入命令。

10. 发明授权

US07196950B2 Non-volatile semiconductor storage device performing ROM read operation upon power-on 有权
标题翻译：上电时执行ROM读取操作的非易失性半导体存储装置
公开(公告)号：US07196950B2
公开(公告)日：2007-03-27
申请号：US11359898
申请日：2006-02-16
申请人： Kazushige Kanda , Hiroshi Nakamura
发明人： Kazushige Kanda , Hiroshi Nakamura
IPC分类号： G11C7/00
CPC分类号： G11C16/20 , G11C16/30
摘要： A power-on reset circuit has a power-on level detecting circuit which detects a power voltage to output a power-on reset signal and a delay circuit which delays the power-on reset signal output by the power-on level detecting circuit. Two chip address specifying pads are connected to the delay circuit. Delay time in the delay time is controlled according to a chip address supplied to these two pads.
摘要翻译：上电复位电路具有检测电源电压以输出上电复位信号的上电电平检测电路和延迟由通电电平检测电路输出的上电复位信号的延迟电路。两个芯片地址指定焊盘连接到延迟电路。根据提供给这两个焊盘的芯片地址来控制延迟时间的延迟时间。

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