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1. 发明授权

US06300229B1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06300229B1
公开(公告)日：2001-10-09
申请号：US09563130
申请日：2000-05-02
申请人： Kazuo Tanaka , Takashi Kumagai , Junichi Karasawa , Kunio Watanabe
发明人： Kazuo Tanaka , Takashi Kumagai , Junichi Karasawa , Kunio Watanabe
IPC分类号： H01L2120
CPC分类号： H01L27/11 , H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/1104
摘要： A method of manufacturing a semiconductor device comprising the following steps: forming first, second, and third wiring layers on a semiconductor substrate; forming first, second, and third cover dielectric layers for covering these wiring layers; forming a first impurity diffusion layer of a P type and a second impurity diffusion layer of an N type in an active region, and forming a third impurity diffusion layer of a P type and a fourth impurity diffusion layer of an N type in an active region; self-alignably forming a first local wiring layer for connecting the first impurity diffusion layer with the second wiring layer, and self-alignably forming a second local wiring layer for connecting the fourth impurity diffusion layer with the third wiring layer; in an interlayer dielectric layer, self-alignably forming a first contact hole by using the first and third cover dielectric layers as masking layers, and self-alignably forming a second contact hole by using the second cover dielectric layer as a masking layer; and forming fourth and fifth wiring layers in these contact holes, respectively.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成第一，第二和第三布线层; 形成用于覆盖这些布线层的第一，第二和第三覆盖电介质层; 在有源区中形成P型和N型的第二杂质扩散层的第一杂质扩散层，在有源区中形成P型的第三杂质扩散层和N型的第四杂质扩散层 ; 自对准地形成用于将第一杂质扩散层与第二布线层连接的第一局部布线层，并自对准地形成用于将第四杂质扩散层与第三布线层连接的第二局部布线层; 在层间电介质层中，通过使用第一和第三覆盖电介质层作为掩蔽层自对准地形成第一接触孔，并且通过使用第二覆盖电介质层作为掩蔽层自对准地形成第二接触孔; 并且在这些接触孔中分别形成第四和第五布线层。

2. 发明授权

US06534864B1 Semiconductor memory device and method of fabricating the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06534864B1
公开(公告)日：2003-03-18
申请号：US09428821
申请日：1999-10-28
申请人： Kazuo Tanaka , Takashi Kumagai , Junichi Karasawa , Kunio Watanabe
发明人： Kazuo Tanaka , Takashi Kumagai , Junichi Karasawa , Kunio Watanabe
IPC分类号： H01L2348
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903
摘要： A semiconductor memory device (SRAM) comprises memory cells, each of which includes two load transistors, two driver transistors and two transfer transistors. The SRAM cell includes a semiconductor substrate in which the transistors are formed, a first interlayer dielectric formed on the semiconductor substrate, first contact portions formed in the first interlayer dielectric and first wiring layers (node wiring layers and pad layers) formed on the first interlayer dielectric. The first contact portions and the first wiring layers include metal layers made of refractory metal and a refractory metal nitride layers. This semiconductor memory device of the present invention is capable of enhancing an integration degree of wiring layers and achieving a microfabrication.
摘要翻译：半导体存储器件（SRAM）包括存储单元，每个存储单元包括两个负载晶体管，两个驱动晶体管和两个转移晶体管。 SRAM单元包括其中形成晶体管的半导体衬底，形成在半导体衬底上的第一层间电介质，形成在第一层间电介质中的第一接触部分和形成在第一层间电介质上的第一布线层（节点布线层和衬垫层）电介质。第一接触部分和第一布线层包括由难熔金属制成的金属层和难熔金属氮化物层。本发明的半导体存储器件能够提高布线层的集成度并实现微细加工。

3. 发明授权

US06232670B1 Semiconductor memory device and method of fabricating the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06232670B1
公开(公告)日：2001-05-15
申请号：US09361043
申请日：1999-07-26
申请人： Takashi Kumagai , Junichi Karasawa , Kazuo Tanaka , Kunio Watanabe
发明人： Takashi Kumagai , Junichi Karasawa , Kazuo Tanaka , Kunio Watanabe
IPC分类号： H01L2711
CPC分类号： H01L27/1104
摘要： First and second memory cells of an SRAM comprises first, second, and third conductive layers. The first conductive layer is a gate electrode for a first load transistor and a first driver transistor. The second conductive layer diverges from the first conductive layer on a field oxide region and is electrically connected to a second driver transistor active region. The third conductive layer is a gate electrode for a second load transistor and a second driver transistor. The third conductive layer is electrically connected to a first load transistor active region. The pattern of the first, second, and third conductive layers of the second memory cell is a rotated pattern of the first, second, and third conductive layers in the first memory cell at an angle of 180 degrees around an axis perpendicular to the main surface of a semiconductor substrate.
摘要翻译： SRAM的第一和第二存储单元包括第一，第二和第三导电层。第一导电层是用于第一负载晶体管和第一驱动晶体管的栅电极。第二导电层从场氧化物区域上的第一导电层发散，并且电连接到第二驱动器晶体管有源区。第三导电层是用于第二负载晶体管的栅电极和第二驱动晶体管。第三导电层电连接到第一负载晶体管有源区。第二存储单元的第一，第二和第三导电层的图案是第一存储单元中的第一，第二和第三导电层的旋转图案，围绕垂直于主表面的轴以180度的角度的半导体衬底。

4. 发明授权

US06243286B1 Semiconductor memory device and method of fabricating the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06243286B1
公开(公告)日：2001-06-05
申请号：US09361095
申请日：1999-07-26
申请人： Takashi Kumagai , Junichi Karasawa , Kazuo Tanaka , Kunio Watanabe
发明人： Takashi Kumagai , Junichi Karasawa , Kazuo Tanaka , Kunio Watanabe
IPC分类号： G11C1100
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903
摘要： An SRAM comprises first, second and third conductive layers. The first conductive layer is a gate electrode for a first load transistor and a first driver transistor. The second conductive layer branches from the first conductive layer on a field oxide region and is electrically connected to a second driver transistor active region. The third conductive layer is a gate electrode for a second load transistor and a second driver transistor. The third conductive layer is electrically connected to a first load transistor active region. The width of part of the second conductive layer on the field oxide region is less than the width of the first conductive layer.
摘要翻译： SRAM包括第一，第二和第三导电层。第一导电层是用于第一负载晶体管和第一驱动晶体管的栅电极。第二导电层在场氧化物区域上从第一导电层分支并且电连接到第二驱动晶体管有源区。第三导电层是用于第二负载晶体管的栅电极和第二驱动晶体管。第三导电层电连接到第一负载晶体管有源区。场氧化物区域上的第二导电层的一部分的宽度小于第一导电层的宽度。

5. 发明授权

US6081016A CMOS device with improved wiring density 有权
标题翻译：具有改善布线密度的CMOS器件
公开(公告)号：US6081016A
公开(公告)日：2000-06-27
申请号：US282035
申请日：1999-03-30
申请人： Kazuo Tanaka , Takashi Kumagai , Junichi Karasawa , Kunio Watanabe
发明人： Kazuo Tanaka , Takashi Kumagai , Junichi Karasawa , Kunio Watanabe
IPC分类号： H01L21/28 , H01L21/285 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11 , H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/1104
摘要： A method of manufacturing a semiconductor device comprising the following steps: forming first, second, and third wiring layers on a semiconductor substrate; forming first, second, and third cover dielectric layers for covering these wiring layers; forming a first impurity diffusion layer of a P type and a second impurity diffusion layer of an N type in an active region, and forming a third impurity diffusion layer of a P type and a fourth impurity diffusion layer cf an N type in an active region; self-alignably forming a first local wiring layer for connecting the first impurity diffusion layer with the second wiring layer, and self-alignably forming a second local wiring layer for connecting the fourth impurity diffusion layer with the third wiring layer; in an interlayer dielectric layer, self-alignably forming a first contact hole by using the first and third cover dielectric layers as masking layers, and self-alignably forming a second contact hole by using the second cover dielectric layer as a masking layer; and forming fourth and fifth wiring layers in these contact holes, respectively.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成第一，第二和第三布线层; 形成用于覆盖这些布线层的第一，第二和第三覆盖电介质层; 在有源区中形成P型和N型的第二杂质扩散层的第一杂质扩散层，在有源区中形成N型的P型和第四杂质扩散层的第三杂质扩散层 ; 自对准地形成用于将第一杂质扩散层与第二布线层连接的第一局部布线层，并自对准地形成用于将第四杂质扩散层与第三布线层连接的第二局部布线层; 在层间电介质层中，通过使用第一和第三覆盖电介质层作为掩蔽层自对准地形成第一接触孔，并且通过使用第二覆盖电介质层作为掩蔽层自对准地形成第二接触孔; 并且在这些接触孔中分别形成第四和第五布线层。

6. 发明授权

US08973253B2 Method and apparatus for manufacturing metal plate chip resistors 有权
标题翻译：制造金属板片式电阻器的方法和装置
公开(公告)号：US08973253B2
公开(公告)日：2015-03-10
申请号：US14074858
申请日：2013-11-08
申请人： Tatsuki Hirano , Kazuo Tanaka
发明人： Tatsuki Hirano , Kazuo Tanaka
IPC分类号： H01C17/00 , H01C17/245
CPC分类号： H01C17/006 , H01C17/245
摘要： The object of the invention is to provide a method and an apparatus that allow production of metal plate chip resistors having a relatively low resistance with high accuracy and yield through simple process. The object is achieved by apparatus for manufacturing metal plate chip resistors including cutting mold for cutting intermediate product strip transversely to obtain worked product chip, ohm meter for measuring the resistance of the worked product chip, control device having a calculating part for performing a calculation using the resistance measured by the ohm meter to work out a width in which the strip is to be cut transversely so as to obtain a worked product chip of a desired resistance, and cutting width adjustor for making an adjustment so that the strip is to be cut transversely in the width obtained from the calculating part.
摘要翻译：本发明的目的是提供一种通过简单的工艺制造具有相对较低电阻的金属板片式电阻器的方法和装置，其具有高精度和高产率。该目的是通过用于制造金属板片电阻器的装置实现的，包括用于横向切割中间产品带的切割模具，以获得加工产品芯片，用于测量加工产品芯片的电阻的欧姆表，具有用于执行计算的计算部分的控制装置由欧姆计测量的电阻以横向切割条的宽度，以获得期望电阻的加工产品芯片，以及用于进行调整的切割宽度调节器，使得条被切割横向于从计算部分获得的宽度。

7. 发明授权

US08590141B2 Method and apparatus for manufacturing metal plate chip resistors 有权
标题翻译：制造金属板片式电阻器的方法和装置
公开(公告)号：US08590141B2
公开(公告)日：2013-11-26
申请号：US13196078
申请日：2011-08-02
申请人： Tatsuki Hirano , Kazuo Tanaka
发明人： Tatsuki Hirano , Kazuo Tanaka
IPC分类号： H01C17/00
CPC分类号： H01C17/006 , H01C17/245
摘要： The object of the invention is to provide a method and an apparatus that allow production of metal plate chip resistors having a relatively low resistance with high accuracy and yield through simple process. The object is achieved by apparatus 10 for manufacturing metal plate chip resistors including cutting mold 21 for cutting intermediate product strip 14 transversely to obtain worked product chip 16a, ohm meter 22 for measuring the resistance of the worked product chip 16a, control device 23 having a calculating part for performing a calculation using the resistance measured by the ohm meter 22 to work out a width in which the strip 14 is to be cut transversely so as to obtain a worked product chip of a desired resistance, and cutting width adjusting means 26, 27 for making an adjustment so that the strip 14 is to be cut transversely in the width obtained from the calculating part.
摘要翻译：本发明的目的是提供一种通过简单的工艺制造具有相对较低电阻的金属板片式电阻器的方法和装置，其具有高精度和高产率。该目的是通过用于制造金属板片式电阻器的装置10实现的，包括用于横向切割中间产品条带14的切割模具21，以获得加工产品芯片16a，用于测量加工产品芯片16a的电阻的欧姆计22，具有使用由欧姆计22测量的电阻进行计算的计算部分，以计算要横向切割条带14的宽度，以获得期望电阻的加工产品芯片;以及切割宽度调节装置26， 27，用于进行调整，使得条带14在从计算部分获得的宽度上横向切割。

8. 发明授权

US08584783B2 Motorcycle with supercharger 有权
标题翻译：带增压器的摩托车
公开(公告)号：US08584783B2
公开(公告)日：2013-11-19
申请号：US13531361
申请日：2012-06-22
申请人： Daisuke Saeki , Kazuo Tanaka
发明人： Daisuke Saeki , Kazuo Tanaka
IPC分类号： B62M27/02
CPC分类号： B62M7/02 , B62K19/30 , F02B33/32 , F02M35/162
摘要： A motorcycle includes a combustion engine (E) of a type, in which a cylinder block (34) protrudes upwardly from a crankcase (32), an air cleaner unit (42) for substantially purifying an air, and a supercharger (44) for taking a substantially purified air from the air cleaner unit (42) thereinto and supplying the air towards the combustion engine (E). The supercharger (44) is disposed rearwardly of the cylinder block (34) and the air cleaner unit (42) is disposed rearwardly thereof. Also, a surge tank (48) is disposed rearwardly upwardly of the cylinder block (34) of the combustion engine (E) and above the supercharger (44).
摘要翻译：摩托车包括一种内燃机（E），其中气缸体（34）从曲轴箱（32）向上突出，用于基本上净化空气的空气滤清器单元（42），以及增压器（44），用于从空气滤清器单元（42）中取出基本上净化的空气并将空气供给到内燃机（E）。增压器（44）设置在气缸体（34）的后方，空气滤清器单元（42）设置在气缸体的后方。此外，缓冲罐（48）设置在内燃机（E）的气缸体（34）的上方的上方并且位于增压器（44）的上方。

9. 发明申请

US20130049864A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20130049864A1
公开(公告)日：2013-02-28
申请号：US13589369
申请日：2012-08-20
申请人： Natsuki IKEHATA , Kazuo Tanaka , Takeo Toba , Masashi Arakawa
发明人： Natsuki IKEHATA , Kazuo Tanaka , Takeo Toba , Masashi Arakawa
IPC分类号： H03F3/45
CPC分类号： G11C11/4091 , G11C7/10 , G11C7/1057 , G11C7/1072 , G11C7/1084 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.
摘要翻译：差分放大电路的输出信号特性得到改善。当输入数据信号为低电平时，流过第一晶体管的电流将减小，并且第一电阻器和第二电阻器之间的连接（节点）的电位将增加。该电位被输入（负反馈）到第二晶体管的栅极，并且由于该栅极电位增加，所以在增加的方向上调节尾部电流量。当输入数据信号为高电平时，第一晶体管的电流增加，因此节点处的电位降低。因此，第二晶体管的栅极电位（负反馈）减小，并且沿着减小的方向调整尾电流量。因此，在输入波形的上升和下降中，延迟时间相对于输出波形的差别分别减小。

10. 发明授权

US08173806B2 Method for production of quinazolin-4-one derivative 失效
标题翻译：喹唑啉-4-酮衍生物的制备方法
公开(公告)号：US08173806B2
公开(公告)日：2012-05-08
申请号：US12282381
申请日：2007-03-14
申请人： Kazuo Tanaka , Yoshifumi Sato , Takafumi Yoshimura
发明人： Kazuo Tanaka , Yoshifumi Sato , Takafumi Yoshimura
IPC分类号： C07D239/72
CPC分类号： C07D239/88
摘要： In reacting an anthranilic acid derivative represented by the general formula (1), especially the anthranilic acid derivative selected from anthranilic acid, anthranilamide and anthranilate, with formamide, the reaction is attained under the condition of coexistence of acetic acid and a base as a catalyst in the reaction liquid, and it has made it possible to produce a quinazolin-4-one derivative represented by the general formula (2) and useful as a material for medicine intermediates, at high yield with no side production.
摘要翻译：在使通式（1）表示的邻氨基苯甲酸衍生物，特别是选自邻氨基苯甲酸，邻氨基苯甲酰胺和邻氨基苯甲酸酯的邻氨基苯甲酸衍生物与甲酰胺反应时，在乙酸和碱作为催化剂共存的条件下反应在反应液中，可以以高产率生产无副产物的由通式（2）表示的喹唑啉-4-酮衍生物作为医药中间体的材料。

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