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1. 发明授权

US4397951A Elastase-containing composition permitting elastase to be absorbed in increased amount 失效
标题翻译：含弹性蛋白酶的组合物允许弹性蛋白酶以增加的量被吸收
公开(公告)号：US4397951A
公开(公告)日：1983-08-09
申请号：US343333
申请日：1982-01-27
申请人： Kazuo Taki , Ryoichi Machida , Kouichi Katayama
发明人： Kazuo Taki , Ryoichi Machida , Kouichi Katayama
IPC分类号： A61K38/46 , A61K38/00 , A61K38/43 , A61K47/26 , A61P3/06 , A61P9/10 , C12N9/66 , C12N9/96 , A61K37/48
CPC分类号： C12N9/6448 , A61K47/26 , A61K38/00
摘要： An elastase-containing composition containing 0.5 to 50 parts by weight of sucrose fatty acid ester per part by weight of pure elastase, which composition permits elastase, useful as medicine for arterioscloerosis and hyperlipemia, to be absorbed in increased amount through intenstine.
摘要翻译：含有0.5〜50重量份蔗糖脂肪酸酯的重量份纯弹性蛋白酶组合物，该组合物允许弹性蛋白酶用作动脉硬化和高脂血症的药物，以通过内脏吸收增加的量。

2. 发明授权

US06329845B1 Logic gate cell 失效
标题翻译：逻辑门单元
公开(公告)号：US06329845B1
公开(公告)日：2001-12-11
申请号：US09333456
申请日：1999-06-15
申请人： Kazuo Taki
发明人： Kazuo Taki
IPC分类号： H01L2500
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/092
摘要： To provide a small-area and low-power-consuming logic gate cell which is constructed of a circuit of two inverting logic gates connected in series in a layout of four-step diffusion regions. A first inverting logic gate is formed of a small transistor on internal two-step diffusion regions, a second inverting logic gate is formed of external two-step diffusion regions, and output wirings of the second inverting logic gate is formed of second metal layer wirings so that the second metal layer wirings extend over the first inverting logic gate.
摘要翻译：提供一种由四步扩散区的布局串联连接的两个反相逻辑门的电路构成的小面积和低功耗的逻辑门单元。第一反相逻辑门由内部两步扩散区域上的小晶体管形成，第二反向逻辑门由外部两步扩散区形成，第二反向逻辑门的输出布线由第二金属层布线使得第二金属层布线在第一反相逻辑门上延伸。

3. 发明授权

US6005418A Low power consuming logic circuit 失效
标题翻译：低功耗逻辑电路
公开(公告)号：US6005418A
公开(公告)日：1999-12-21
申请号：US763743
申请日：1996-12-11
申请人： Kazuo Taki
发明人： Kazuo Taki
IPC分类号： H03K17/16 , H03K17/687 , H03K19/00 , H03K19/0948 , H03K19/096 , H03K19/094
CPC分类号： H03K19/0016 , H03K19/0963
摘要： Disclosed is a low power consuming logic circuit to restrain a short circuit current which flows within an inverter circuit of an inverter having a clock input connected behind a pass-transistor logic circuit. In the logic circuit, the inverter having a clock input is provided on the output of a pass-transistor logic circuit. The inverter having a clock input includes the inverter circuit and write control means. A data holding circuit is connected to the output of the write control means. In the logic circuit, a clock is input to the inverter having a clock input after the output of the pass-transistor logic circuit is stabilized. Thus, the short circuit current which flows in the inverter circuit is restrained. In addition to the logic circuit, a positive feedback circuit for supplying an inverted signal from the inverter circuit to the output of the inverter having a clock input can be provided. In the logic circuit, the positive feedback circuit functions to further increase the voltage of the output signal of the pass-transistor logic circuit if it is higher than the input threshold of the inverter, and to further reduce the same voltage if it is lower than the input threshold of the inverter. Consequently, the short circuit current flows in the inverter having a clock input in a very short time.
摘要翻译：公开了一种低功耗逻辑电路，用于抑制在具有连接在传输晶体管逻辑电路后面的时钟输入的反相器的反相器电路内流动的短路电流。在逻辑电路中，具有时钟输入的反相器设置在传输晶体管逻辑电路的输出端。具有时钟输入的逆变器包括逆变器电路和写入控制装置。数据保持电路连接到写入控制装置的输出。在逻辑电路中，在通过晶体管逻辑电路的输出稳定之后，时钟输入到具有时钟输入的反相器。因此，抑制在逆变器电路中流动的短路电流。除了逻辑电路之外，还可以提供用于将来自逆变器电路的反相信号提供给具有时钟输入的反相器的输出的正反馈电路。在逻辑电路中，如果反馈电路的输入阈值高于反相器的输入阈值，则正反馈电路用于进一步增加通过晶体管逻辑电路的输出信号的电压，如果低于逆变器的输入阈值。因此，短路电流在非常短的时间内具有时钟输入的逆变器中流动。

4. 发明授权

US4325942A Ubidecarenone compositions having enhanced absorption properties 失效
标题翻译：具有增强的吸收性能的乌尼可龙酮组合物
公开(公告)号：US4325942A
公开(公告)日：1982-04-20
申请号：US169194
申请日：1980-07-15
申请人： Kazuo Taki , Hideo Takahira
发明人： Kazuo Taki , Hideo Takahira
IPC分类号： A61K9/20 , A61K31/12 , A61K31/23 , A61K47/12 , A61K47/14 , A61K37/48
CPC分类号： A61K31/23 , A61K31/12 , A61K47/12 , A61K47/14 , A61K9/2013
摘要： A novel ubidecarenone composition comprising ubidecarenone and higher fatty acid(s) or monoglyceride(s) of higher fatty acid(s), or a mixture thereof, which has improved absorptivity through the lymphatic duct.
摘要翻译：一种新颖的乌替克莱隆组合物，其包含通过淋巴管改善的吸收性的二萜烯壬醇和高级脂肪酸或高级脂肪酸的单甘油酯或其混合物。

5. 发明申请

US20120305899A1 POLYMER COMPOUND, AND THIN FILM AND INK COMPOSITION EACH CONTAINING SAME 有权
标题翻译：聚合物化合物，和薄膜和墨水组合物，每个包含它们
公开(公告)号：US20120305899A1
公开(公告)日：2012-12-06
申请号：US13518671
申请日：2010-12-22
申请人： Kazuo Taki , Itaru Osaka , Kenji Kohiro , Kenichiro Ohya , Kunihito Miyake
发明人： Kazuo Taki , Itaru Osaka , Kenji Kohiro , Kenichiro Ohya , Kunihito Miyake
IPC分类号： C08G75/00 , C09D11/00 , C09D181/00 , H01L51/46 , C08G75/32
CPC分类号： H01L51/0036 , C08G61/126 , C08G2261/3223 , C08G2261/3243 , C08G2261/411 , C08G2261/414 , C08G2261/51 , C08G2261/92 , H01L51/0043 , H01L51/0541 , H01L51/0545 , H01L51/0558 , Y02E10/52 , Y02E10/549
摘要： An object of the present invention is to provide a polymer compound providing high charge mobility. The polymer compound of the present invention has a repeating unit represented by the formula (1): wherein Ar1 and Ar2 are each an aromatic hydrocarbon ring, a heterocycle, or a fused ring of an aromatic hydrocarbon ring and a heterocycle; and R1, R2, R3 and R4 each represent a hydrogen atom, an alkyl group, an alkoxy group, an alkylthio group, an aryl group, an aryloxy group, an arylthio group, an arylalkyl group, an arylalkoxy group, an arylalkylthio group, a substituted silyl group, an unsubstituted or substituted carboxyl group, a monovalent heterocyclic group, a cyano group or a fluorine atom.
摘要翻译：本发明的目的是提供提供高电荷迁移率的高分子化合物。本发明的高分子化合物具有式（1）表示的重复单元：其中Ar 1和Ar 2分别为芳香族烃环，杂环或芳香族烃环和杂环的稠环; R 1，R 2，R 3和R 4各自表示氢原子，烷基，烷氧基，烷硫基，芳基，芳氧基，芳硫基，芳烷基，芳烷氧基，芳烷硫基，取代甲硅烷基，未取代或取代的羧基，1价杂环基，氰基或氟原子。

6. 发明授权

US06509761B2 Logical circuit 失效
公开(公告)号：US06509761B2
公开(公告)日：2003-01-21
申请号：US09991153
申请日：2001-11-13
申请人： Kazuo Taki
发明人： Kazuo Taki
IPC分类号： H03K1920
CPC分类号： G06F7/5016 , H03K19/0948 , H03K19/0963
摘要： Very high speed operation and reduction of power consumption are realized simultaneously in a two-wire type logical circuit having a halt value and an effective value as signal values. Signal rise transition delay time and signal fall transition delay time are purposely designed asymmetrically and an effective value propagation delay is shortened, thereby accelerating an operating speed of the logical circuit. By eliminating a clock signal from a DOMINO circuit, power consumption is reduced. An architecture for concealing a halt value propagation delay is employed.

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