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1. 发明授权

US06563194B1 BJT with surface resistor connection 失效
标题翻译： BJT带表面电阻连接
公开(公告)号：US06563194B1
公开(公告)日：2003-05-13
申请号：US09666848
申请日：2000-09-21
申请人： Kazuhisa Sakamoto
发明人： Kazuhisa Sakamoto
IPC分类号： H01L27082
CPC分类号： H01L27/0658 , H01L29/7304
摘要： A semiconductor device having: a base area of the first conduction type formed on a semiconductor substrate; an emitter area of the second conduction type formed in the base area; and a collector area of the second conduction type formed as joined to the base area. In the collector area, an impurity area of the first conduction type is formed as separated from the base area. A surface resistor is connected to a base electrode connected to the base area. The surface resistor is connected, at other position thereof, to the impurity area.
摘要翻译：一种半导体器件，具有：在半导体衬底上形成的第一导电类型的基极区域; 形成在基部区域中的第二导电类型的发射极区域; 以及形成为接合到基部区域的第二导电类型的集电极区域。在集电极区域中，形成与基极区域分离的第一导电类型的杂质区域。表面电阻器连接到连接到基座区域的基极。表面电阻器的其他位置连接到杂质区域。

2. 发明授权

US08060244B2 Substrate processing apparatus and carrier adjusting system 有权
标题翻译：基板加工装置和载体调整系统
公开(公告)号：US08060244B2
公开(公告)日：2011-11-15
申请号：US11889923
申请日：2007-08-17
申请人： Takashi Aiuchi , Akihito Suzuki , Hirotsugu Kamamoto , Shuichi Yonemura , Takashi Imafu , Kazuhisa Sakamoto
发明人： Takashi Aiuchi , Akihito Suzuki , Hirotsugu Kamamoto , Shuichi Yonemura , Takashi Imafu , Kazuhisa Sakamoto
IPC分类号： G06F7/00
CPC分类号： H01L21/67276
摘要： An object of the present invention is to perform replacement of parts of a substrate processing apparatus more rapidly than that by the prior art. The present invention is a substrate processing apparatus constituted of a plurality of component parts for performing predetermined processing for a substrate, identification marks being attached to the respective component parts, the apparatus including: a storage unit for storing part information on each of the component parts necessary when placing an order for a component part, in correspondence with the identification mark; an input unit for inputting an identification mark of a component part to be ordered; and a display unit for displaying the part information in the storage unit corresponding to the inputted identification mark.
摘要翻译：本发明的目的是比现有技术更快地更换基板处理装置的部件。本发明是一种由多个用于对基板进行预定处理的部件构成的基板处理装置，识别标记附着在各个部件上，该装置包括：存储单元，用于存储关于每个部件的部件信息在与识别标记对应的情况下，对组件部分进行订购时必要; 用于输入要订购的部件的识别标记的输入单元; 以及显示单元，用于在与输入的识别标记相对应的存储单元中显示零件信息。

3. 发明申请

US20060151829A1 Semiconductor device and a method for manufacturing therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060151829A1
公开(公告)日：2006-07-13
申请号：US11371720
申请日：2006-03-09
申请人： Kazuhisa Sakamoto
发明人： Kazuhisa Sakamoto
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L21/263 , H01L29/32 , H01L29/41741 , H01L29/66333 , H01L29/66348 , H01L29/7395
摘要： An object of the present invention is to provide a semiconductor device capable of radiating electron-beams only to a desired region without forming a layer for restricting the radiating rays. A source electrode 22 made of aluminum prevents the generation of bremsstrahlung even when the electron-beams are radiated to the source electrode in a exposed condition. Also, the source electrode having an opening 25 at above of a crystal defect region 11 is used as a mask when the electron-beams are radiated thereto. That is the source electrode made of aluminum can be used both as a wiring and a mask for the radiating rays.
摘要翻译：本发明的目的是提供一种能够仅将电子束辐射到所需区域而不形成用于限制辐射光线的层的半导体器件。即使当电子束在暴露状态下被辐射到源电极时，由铝制成的源电极22也防止产生bre致辐射。此外，当电子束辐射到其上时，具有在晶体缺陷区域11的上方的开口25的源电极被用作掩模。也就是说，由铝制成的源极可以用作布线和用于辐射光线的掩模。

4. 发明授权

US08482539B2 Electronic pen system 有权
标题翻译：电子笔系统
公开(公告)号：US08482539B2
公开(公告)日：2013-07-09
申请号：US12987334
申请日：2011-01-10
申请人： Toshiyuki Ogawa , Toshihito Tanaka , Kazuhisa Sakamoto , Tatsuhito Ueno , Yuuji Toyomura
发明人： Toshiyuki Ogawa , Toshihito Tanaka , Kazuhisa Sakamoto , Tatsuhito Ueno , Yuuji Toyomura
IPC分类号： G06F3/041
CPC分类号： G06F3/0488 , G06F3/03545 , G06F3/044 , G06F2203/04104
摘要： An electronic pen transmits pen information to a controller corresponding to detection of a touch condition, and thereafter turns ON a connecting switch that disconnects electrical connection between the tip portion and the grip portion of the pen that are provided in a state of being electrically disconnected from each other so as to cause a pen input acceptance state. The controller determines that position detection information is from the electronic pen when the position detection information is received from a position detecting device after the pen information is received from the electronic pen, while the controller determines that position detection information is from a finger when the position detection information is received from the position detecting device without receiving the pen information from the electronic pen.
摘要翻译：电子笔将触摸条件的笔信息发送到控制器，然后接通一个连接开关，该连接开关断开在与电气断开的状态下设置的笔尖部分和握持部分之间的电连接以使笔输入接受状态。当从电子笔接收到笔信息之后，当从位置检测装置接收到位置检测信息时，控制器确定位置检测信息来自电子笔，同时当位置检测信息由手指确定位置检测信息时，从位置检测装置接收到来自电子笔的笔信息的检测信息。

5. 发明授权

US06747315B1 Semiconductor device having MOS field-effect transistor 有权
标题翻译：具有MOS场效应晶体管的半导体器件
公开(公告)号：US06747315B1
公开(公告)日：2004-06-08
申请号：US10030089
申请日：2002-01-14
申请人： Kazuhisa Sakamoto
发明人： Kazuhisa Sakamoto
IPC分类号： H01L2976
CPC分类号： H01L29/7805 , H01L29/0696 , H01L29/1095 , H01L29/7806 , H01L29/7811
摘要： P-wells (21) are formed in, for example, a matrix in an N-type semiconductor layer (20). At an outer periphery of each of the P-wells (21) is formed, for example, a rectangular ring-shaped N+-type diffused source region (22), between which and an N-type semiconductor layer (20) which provides a drain region (23) is formed a channel region (26). A source electrode (33) is formed in such a manner as to be contact with the center portion of each of the P-wells (21) and the source region (22) in such a construction that a contact portion (40) of the P-well with the source electrode consists of P+-type regions and N+-type regions formed alternately. As a result, it is possible to rapidly eliminate the minority carrier generated in the P-well owing to a counter electromotive force etc., thus speeding the switching operations.
摘要翻译： P阱（21）形成在例如N型半导体层（20）中的矩阵中。在每个P阱（21）的外周形成例如矩形的N +型N +型扩散源极区（22），N型半导体层（20）与N型半导体层其提供漏极区（23）形成沟道区（26）。源电极（33）以与每个P阱（21）和源极区（22）的中心部分接触的方式形成为这样的结构：使得接触部分源电极的P阱由交替形成的P +型区域和N +型区域组成。结果，可以通过反电动势等快速地消除在P阱中产生的少数载流子，从而加速切换操作。

6. 发明授权

US06740907B2 Junction field-effect transistor 有权
标题翻译：结场效应晶体管
公开(公告)号：US06740907B2
公开(公告)日：2004-05-25
申请号：US10263800
申请日：2002-10-04
申请人： Kazuhisa Sakamoto
发明人： Kazuhisa Sakamoto
IPC分类号： H01L2974
CPC分类号： H01L29/41725 , H01L29/42316 , H01L29/808
摘要： A junction field-effect transistor is formed by providing a p-type gate region in a surface of an n-type semiconductor layer and n-type drain and source regions sandwiching the gate region on the surface of the n-type semiconductor layer. A p-type diffusion region is formed at least in the region on the side of the drain close to the gate region on the surface of the n-type semiconductor layer. A drain electrode is formed so that it contacts with the p-type diffusion region. As a result, the junction FET can be reduced in drain-source leak current Idss to a small, stable value. Thus, a high-gain junction field-effect transistor is obtained which has small variation in performance among actual units manufactured.
摘要翻译：通过在n型半导体层的表面上设置p型栅极区域和在n型半导体层的表面上夹持栅极区域的n型漏极和源极区域来形成结型场效应晶体管。至少在靠近n型半导体层的表面上的栅极区域的漏极侧的区域中形成p型扩散区。漏极形成为与p型扩散区接触。结果，可以将漏极 - 源极泄漏电流Idss中的结FET减小到一个小的稳定值。因此，获得了在制造的实际单元中性能变化小的高增益结型场效应晶体管。

7. 发明授权

US5841181A Semiconductor apparatus having field limiting rings 失效
标题翻译：具有场限制环的半导体装置
公开(公告)号：US5841181A
公开(公告)日：1998-11-24
申请号：US716412
申请日：1996-09-20
申请人： Kazuhisa Sakamoto
发明人： Kazuhisa Sakamoto
IPC分类号： H01L29/73 , H01L21/331 , H01L21/761 , H01L29/06 , H01L29/732 , H01L29/74 , H01L29/78 , H01L29/861 , H01L23/58 , H01L27/082
CPC分类号： H01L29/7322 , H01L29/0619 , H01L2924/0002
摘要： It is an object to provide a semiconductor apparatus having improved dielectric breakdown strength characteristics both by eliminating the discontinuity caused to the interface between a semiconductor layer and the overlying insulator film on account of the FLR provided for increasing the dielectric breakdown strength and by preventing the redistribution of impurities from the FLR into the insulator film. Another object is to provide a process for fabricating such improved semiconductor apparatus. The semiconductor layers of a first conduction type (i.e., n.sup.- type semiconductor layer 1b and epitaxial layer 1c) are provided with the semiconductor region of a second conduction type (i.e., p-type base region 2) to form a semiconductor device (transistor) and FLRs 4a and 4b are provided external to the perimeter of said semiconductor region but without being exposed from the surface of the epitaxial layer 1c.
摘要翻译： PCT No.PCT / JP96 / 00367 Sec。 371日期：1996年9月20日 102（e）1996年9月20日PCT PCT 1996年2月19日PCT公布。公开号WO96 / 26547 日期为1996年8月29日的目的在于提供一种具有改善的介电击穿强度特性的半导体装置，其特征在于，通过消除由于为提高介电击穿强度而提供的FLR而导致的半导体层与上覆绝缘膜之间的界面的不连续性并且通过防止杂质从FLR再分配到绝缘膜中。另一个目的是提供一种用于制造这种改进的半导体装置的方法。第一导电类型（即n型半导体层1b和外延层1c）的半导体层设置有第二导电类型（即，p型基极区域2）的半导体区域，以形成半导体器件（晶体管）和FLR 4a和4b设置在所述半导体区域的周边的外部，但不暴露于外延层1c的表面。

8. 发明授权

US5808352A Semiconductor apparatus having crystal defects 失效
标题翻译：具有晶体缺陷的半导体装置
公开(公告)号：US5808352A
公开(公告)日：1998-09-15
申请号：US716420
申请日：1996-09-20
申请人： Kazuhisa Sakamoto
发明人： Kazuhisa Sakamoto
IPC分类号： H01L21/26 , H01L21/263 , H01L21/322 , H01L21/329 , H01L21/331 , H01L21/336 , H01L29/32 , H01L29/73 , H01L29/732 , H01L29/78 , H01L29/861 , H01L29/74 , H01L27/082 , H01L29/30
CPC分类号： H01L29/78 , H01L21/26 , H01L21/263 , H01L29/32 , H01L29/73 , H01L29/7322 , H01L29/7802
摘要： It is an object to provide a semiconductor apparatus having both fast switching characteristics and high dielectric breakdown strength or small leakage current characteristics, as well as a process for fabricating such improved semiconductor apparatus. The apparatus comprises a semiconductor substrate; a semiconductor layer on said semiconductor substrate, said semiconductor layer having a pn junction formed along the surface of said semiconductor substrate, wherein crystal defects being formed by irradiation with particle rays to the only vertical direction of said pn junction; and a silicon nitride film provided on the substrate surface of said layer for restraining the exposure to particle rays being provided on the substrate surface of said element in the areas other than said pn junction.
摘要翻译： PCT No.PCT / JP96 / 00368 Sec。 371日期：1996年9月20日 102（e）1996年9月20日PCT PCT 1996年2月19日PCT公布。公开号WO96 / 26536 日期为1996年8月29日的目的在于提供具有快速开关特性和高介电击穿强度或小漏电流特性的半导体装置，以及制造这种改进的半导体装置的方法。该装置包括半导体衬底; 在所述半导体衬底上的半导体层，所述半导体层具有沿着所述半导体衬底的表面形成的pn结，其中通过用所述pn结的唯一垂直方向照射粒子射线形成晶体缺陷; 以及设置在所述层的衬底表面上的氮化硅膜，用于抑制在所述pn结以外的区域中的所述元件的衬底表面上提供的颗粒射线的暴露。

9. 发明申请

US20120003420A1 HONEYCOMB STRUCTURE BODY AND METHOD OF PRODUCING THE SAME 审中-公开
标题翻译：蜂窝结构体及其生产方法
公开(公告)号：US20120003420A1
公开(公告)日：2012-01-05
申请号：US13175080
申请日：2011-07-01
申请人： Takahiro Betsushiyo , Hiromasa Aoki , Kazuhisa Sakamoto
发明人： Takahiro Betsushiyo , Hiromasa Aoki , Kazuhisa Sakamoto
IPC分类号： B32B3/12 , B05D3/02
CPC分类号： C04B35/573 , C04B37/005 , C04B2235/422 , C04B2235/79 , C04B2235/80 , C04B2237/083 , C04B2237/365 , F01N3/2828 , F01N3/2882 , F01N2240/16 , Y10T428/24149
摘要： A honeycomb structure body has a honeycomb base body and a pair of electrodes composed of conductive ceramic layers and intermediate layers. The honeycomb base body made of porous ceramics containing SiC is comprised of a cell formation part and an outer peripheral part. The outer peripheral part covers the cell formation part. Each electrode is comprised of a conductive ceramic layer and an intermediate layer. The conductive ceramic layers containing SiC, Si and C are formed at two opposite positions on the outer peripheral part observed from a diameter direction. The intermediate layers containing SiC, Si and C are formed in the outer peripheral part at the parts which face the conductive ceramic layers. The honeycomb structure body satisfies a relationship of 0.5≦t/T≦1, where “t” indicates the thickness of the intermediate layer and “T” indicates the thickness of the outer peripheral part.
摘要翻译：蜂窝结构体具有蜂窝状基体和由导电性陶瓷层和中间层构成的一对电极。由含有SiC的多孔陶瓷制成的蜂窝状基体由电池形成部和外周部构成。外周部覆盖电池形成部。每个电极由导电陶瓷层和中间层组成。包含SiC，Si和C的导电陶瓷层形成在从直径方向观察的外周部分的两个相对位置处。在面向导电陶瓷层的部分的外周部分中形成含有SiC，Si和C的中间层。蜂窝结构体满足0.5＆nlE; t / T＆nlE; 1的关系，其中“t”表示中间层的厚度，“T”表示外周部的厚度。

10. 发明申请

US20070293970A1 Substrate processing apparatus and carrier adjusting system 有权
标题翻译：基板加工装置和载体调整系统
公开(公告)号：US20070293970A1
公开(公告)日：2007-12-20
申请号：US11889923
申请日：2007-08-17
申请人： Takashi Aiuchi , Akihito Suzuki , Hirotsugu Kamamoto , Shuichi Yonemura , Takashi Imafu , Kazuhisa Sakamoto
发明人： Takashi Aiuchi , Akihito Suzuki , Hirotsugu Kamamoto , Shuichi Yonemura , Takashi Imafu , Kazuhisa Sakamoto
IPC分类号： G06F17/00
CPC分类号： H01L21/67276
摘要： An object of the present invention is to perform replacement of parts of a substrate processing apparatus more rapidly than that by the prior art. The present invention is a substrate processing apparatus constituted of a plurality of component parts for performing predetermined processing for a substrate, identification marks being attached to the respective component parts, the apparatus including: a storage unit for storing part information on each of the component parts necessary when placing an order for a component part, in correspondence with the identification mark; an input unit for inputting an identification mark of a component part to be ordered; and a display unit for displaying the part information in the storage unit corresponding to the inputted identification mark.
摘要翻译：本发明的目的是比现有技术更快地更换基板处理装置的部件。本发明是一种由多个用于对基板进行预定处理的部件构成的基板处理装置，识别标记附着在各个部件上，该装置包括：存储单元，用于存储关于每个部件的部件信息在与识别标记对应的情况下，对组件部分进行订购时必要; 用于输入要订购的部件的识别标记的输入单元; 以及显示单元，用于在与输入的识别标记相对应的存储单元中显示零件信息。

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