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1. 发明授权

US06604232B2 High-level synthesis method and storage medium storing the same 失效
标题翻译：高级合成方法和存储介质的存储介质
公开(公告)号：US06604232B2
公开(公告)日：2003-08-05
申请号：US09741057
申请日：2000-12-21
申请人： Kazuhisa Okada , Koichi Nishida
发明人： Kazuhisa Okada , Koichi Nishida
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A high-level synthesis method comprising the steps of converting an operating description describing one or more operations to a control data flow graph (CDFG) including one or more nodes representing the one or more operations and one or more I/O branches representing a flow of data, scheduling the CDFG obtained by the converting step, and allocating one or more logic circuits required for executing the CDFG obtained by the scheduling step. A portion of the CDFG in the converting step is subjected to logical synthesis in advance to generate a node, and the portion of the CDFG is replaced with that node.
摘要翻译：一种高级合成方法，包括以下步骤：将描述一个或多个操作的操作描述转换成包括表示所述一个或多个操作的一个或多个节点的控制数据流图（CDFG）和表示流程的一个或多个I / O分支调度通过转换步骤获得的CDFG，并分配执行由调度步骤获得的CDFG所需的一个或多个逻辑电路。转换步骤中的CDFG的一部分预先进行逻辑合成以生成节点，并且将该部分的CDFG替换为该节点。

2. 发明授权

US06532584B1 Circuit synthesis method 失效
标题翻译：电路合成方法
公开(公告)号：US06532584B1
公开(公告)日：2003-03-11
申请号：US09709294
申请日：2000-11-13
申请人： Koichi Nishida , Kazuhisa Okada
发明人： Koichi Nishida , Kazuhisa Okada
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A circuit synthesis method includes the steps of converting a behavioral description describing a behavior of calculation processing into a control data flowgraph; assigning a plurality of calculations, at least one input and at least one output in the control data flowgraph into a plurality of prescribed time slots; assigning the plurality of calculations, a plurality of data dependency edges, the at least one input and the at least one output respectively to a plurality of calculation devices, at least one register, at least one input pin and at least one output pin; generating a plurality of paths corresponding to the plurality of data dependency edges; detecting a feedback loop formed of at least two of the plurality of paths and at least one of the plurality of calculation devices; and re-assigning one calculation, which has been assigned to a first calculation device included in the feedback loop, to a second calculation device among the plurality of calculation devices, so as to delete the feedback loop.
摘要翻译：电路合成方法包括将描述计算处理的行为的行为描述转换为控制数据流程图的步骤; 在控制数据流程图中分配多个计算，至少一个输入和至少一个输出到多个规定的时隙中; 将多个计算，多个数据依赖边缘，至少一个输入和至少一个输出分别分配给多个计算装置，至少一个寄存器，至少一个输入引脚和至少一个输出引脚; 产生对应于所述多个数据依赖性边缘的多个路径; 检测由所述多个路径中的至少两个路径和所述多个计算设备中的至少一个组成的反馈回路; 并将已经分配给包括在反馈回路中的第一计算装置的一个计算重新分配给多个计算装置中的第二计算装置，以便删除反馈回路。

3. 发明授权

US06704914B2 High level synthesis method, thread generated using the same, and method for generating circuit including such threads 失效
标题翻译：高级合成方法，使用其生成的线程，以及包括这种线程的电路生成方法
公开(公告)号：US06704914B2
公开(公告)日：2004-03-09
申请号：US10195740
申请日：2002-07-16
申请人： Koichi Nishida , Kazuhisa Okada
发明人： Koichi Nishida , Kazuhisa Okada
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A high level synthesis method for generating a logic circuit of a register transfer level from an operation description includes a control data flowgraph generation stage; a scheduling stage; an allocation stage; a data path generation stage; and a control logic generation stage. When generating a thread sharing a common memory with another thread operating in parallel therewith, a memory access request is represented by a node of a control data flowgraph so as to perform scheduling, and a control logic is generated. The control logic outputs a memory access request signal to a common memory interface in a state corresponding to a step to which the node is scheduled, and keeps the state until a memory access request acceptance signal from the common memory interface is changed to be active.
摘要翻译：用于从操作描述生成寄存器传送电平的逻辑电路的高级合成方法包括控制数据流程图生成级; 调度阶段; 分配阶段数据路径生成阶段; 和控制逻辑生成阶段。当生成与其并行操作的另一个线程共享公共存储器的线程时，存储器访问请求由控制数据流程图的节点表示，以便执行调度，并且产生控制逻辑。控制逻辑以对应于节点被调度的步骤的状态向公共存储器接口输出存储器访问请求信号，并保持该状态，直到来自公共存储器接口的存储器访问请求接收信号被改变为有效。

4. 发明授权

US06505340B2 Circuit synthesis method 失效
标题翻译：电路合成方法
公开(公告)号：US06505340B2
公开(公告)日：2003-01-07
申请号：US09728075
申请日：2000-12-04
申请人： Koichi Nishida , Kazuhisa Okada
发明人： Koichi Nishida , Kazuhisa Okada
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A circuit synthesis method includes the steps of converting a behavioral description describing a behavior of calculation processing into a control data flowgraph; assigning at least one calculation, at least one input and at least one output in the control data flowgraph into prescribed time slots; assigning the at least one calculation, a plurality of data dependency edges, the at least one input and the at least one output respectively to at least one calculation device, at least one register, at least one input pin and at least one output pin; generating a plurality of paths corresponding to the plurality of data dependency edges; and detecting a first false path among the plurality of paths.
摘要翻译：电路合成方法包括将描述计算处理的行为的行为描述转换为控制数据流程图的步骤; 在控制数据流程图中将至少一个计算，至少一个输入和至少一个输出分配到规定的时隙中; 将至少一个计算，多个数据依赖性边缘，所述至少一个输入和至少一个输出分别分配给至少一个计算装置，至少一个寄存器，至少一个输入引脚和至少一个输出引脚; 产生对应于所述多个数据依赖性边缘的多个路径; 以及检测所述多个路径中的第一假路径。

5. 发明授权

US08315579B2 Semiconductor integrated circuit for communication 有权
标题翻译：半导体集成电路通讯
公开(公告)号：US08315579B2
公开(公告)日：2012-11-20
申请号：US12917135
申请日：2010-11-01
申请人： Ryoji Furuya , Kazuhisa Okada , Hiroaki Matsui
发明人： Ryoji Furuya , Kazuhisa Okada , Hiroaki Matsui
IPC分类号： H04B1/04 , H04B1/00
CPC分类号： H03D3/007 , H03C3/40 , H03D7/1433 , H04B1/406
摘要： The present invention provides a semiconductor integrated circuit for communication (RF IC) realizing high yield without deteriorating a carrier leak characteristic even when a modulation circuit is formed by using cheep parts with large variations. In a semiconductor integrated circuit (RF IC) including: an input circuit constructed by a differential amplifier circuit and a level shifter, which is provided on the ante stage of a mixer of a differential circuit called a Gilbert Cell; and a modulation circuit that performs modulation by adding an I/Q signal and a carrier wave signal, a calibration circuit for canceling a DC offset in an output of the input circuit is provided.
摘要翻译：本发明提供了一种用于通信（RF IC）的半导体集成电路，即使在通过使用具有大变化的尖峰部分形成调制电路时，也能实现高产率而不劣化载波泄漏特性。一种半导体集成电路（RF IC），包括：由差分放大电路和电平移位器构成的输入电路，其设置在称为吉尔伯特细胞的差分电路的混频器的前端; 以及通过添加I / Q信号和载波信号来执行调制的调制电路，提供了用于消除输入电路的输出中的DC偏移的校准电路。

6. 发明申请

US20060148768A1 Vitamin d3 lactone derivatives 有权
标题翻译：维生素d3内酯衍生物
公开(公告)号：US20060148768A1
公开(公告)日：2006-07-06
申请号：US10543881
申请日：2004-01-29
申请人： Kazuya Takenouchi , Miyuki Anzai , Hiroshi Saito , Kazuhisa Okada , Seiichi Ishizuka , Daishiro Miura , Hiroaki Takayama , Atsushi Kittaka , Nozomi Saito , Toshie Fujishima
发明人： Kazuya Takenouchi , Miyuki Anzai , Hiroshi Saito , Kazuhisa Okada , Seiichi Ishizuka , Daishiro Miura , Hiroaki Takayama , Atsushi Kittaka , Nozomi Saito , Toshie Fujishima
IPC分类号： A61K31/59 , C07D307/02
CPC分类号： C07D307/58 , A61K31/593
摘要： A compound represented by the following Formula (1) that is effective for the treatment of Paget's disease of bone or hypercalcemia or a medically acceptable solvate thereof; [wherein R1 refers to hydrogen atom, C1-C6 alkyl group optionally substituted with hydrogen group or C1-C6 alkoxy group optionally substituted with hydroxyl group, R2a and R2b refer to hydrogen atom, C1-C10 alkyl group optionally substituted with hydroxyl group, C6-C10 aryl group optionally substituted with hydroxyl group or C7-C12 aralkyl group optionally substituted with a hydroxyl group, or are combined to represent ethylene group. However, a compound in which R1 is a hydrogen atom or a methyl group and R2a and R2b are hydrogen atoms is excluded].
摘要翻译：由下式（1）表示的化合物可有效治疗佩吉特氏骨或高钙血症或其医学上可接受的溶剂合物; [其中R 1是氢原子，任选被氢或C 1 -C 6烷基取代的C 1 -C 6烷基，任选被羟基取代的C 1 -C 6烷氧基，R 2a和R 2b是指氢原子，C 1〜任选被羟基取代的C 1 -C 10烷基，任选被羟基取代的C 6 -C 10芳基或C 6 - 任选被羟基取代的或者被组合以代表亚乙基的C 1 -C 12芳烷基。但是，不包括其中R 1是氢原子或甲基，R 2b和R 2b的氢原子的化合物。

7. 发明申请

US20060130029A1 Programming language model generating apparatus for hardware verification, programming language model generating method for hardware verification, computer system, hardware simulation method, control program and computer-readable storage medium 审中-公开
标题翻译：用于硬件验证的编程语言模型生成装置，用于硬件验证的编程语言模型生成方法，计算机系统，硬件仿真方法，控制程序和计算机可读存储介质
公开(公告)号：US20060130029A1
公开(公告)日：2006-06-15
申请号：US11272712
申请日：2005-11-15
申请人： Takahiro Morishita , Kazuhisa Okada
发明人： Takahiro Morishita , Kazuhisa Okada
IPC分类号： G06F9/45
CPC分类号： G06F17/5045
摘要： The CDFG is generated by the CDFG generating section 109 based on the operation description of hardware 107, the CDFG is scheduled by the scheduling section 110 at an operation frequency required as the specification of the hardware and is assigned to each state, and the operation model of the hardware is generated by the cycle accurate model generating section 111 for each state as a description represented by a general-purpose programming language. The model which can be simulated for each state is generated by generating the operation model of each node using the operation information of the nodes included in the CDFG, and by determining the order in which the operation model of each node is calculated using the connection information of the nodes. As a result, it is possible to generate a model for verification described in a general-purpose programming language, which is capable of verifying hardware at a cycle accurate level at a lower cost and at a higher speed, with a smaller amount of calculation compared with the conventional method.
摘要翻译： CDFG由CDFG生成部109基于硬件107的动作描述生成，由调度部110以作为硬件的规格所要求的运算频率调度CDFG，分配给各状态，运算模型作为由通用编程语言表示的描述，由每个状态的周期精确模型生成部111生成硬件。可以通过使用包括在CDFG中的节点的操作信息生成每个节点的操作模型，并且通过使用连接信息来确定计算每个节点的操作模型的顺序来生成可以针对每个状态来模拟的模型的节点。结果，可以生成用于以通用编程语言描述的验证模型，该通用编程语言能够以较低的成本和更高的速度以更低的计算量对循环精确的级别进行硬件验证用常规方法。

8. 发明申请

US20050165872A1 Method for designing arithmetic device allocation 失效
标题翻译：设计算术装置分配的方法
公开(公告)号：US20050165872A1
公开(公告)日：2005-07-28
申请号：US11088907
申请日：2005-03-25
申请人： Kazuhisa Okada
发明人： Kazuhisa Okada
IPC分类号： G06F7/48 , G06F17/50 , G06F13/00
CPC分类号： G06F17/5045 , G06F7/48
摘要： An arithmetic device allocation design method of the present invention includes the steps of: in the case of allocating an arithmetic operation A to the arithmetic device, comparing an increased circuit area due to a selector to be provided so as to allocate the operation A to an arithmetic device C to which another arithmetic operation B has already been allocated and an increased area due to an arithmetic device D to be created anew to which only the operation A is allocated; when the increased circuit area due to the selector is smaller, allocating the operation A to the device C to which the another operation B has already been allocated while providing the selector; and when the increased circuit area due to the device D is smaller, creating the device D anew so as to allocate the operation A to the device D created anew.
摘要翻译：本发明的算术装置分配设计方法包括以下步骤：在将算术运算A分配给运算装置的情况下，比较由于要提供的选择器而增加的电路面积，以将操作A分配给已经分配了另一算术运算B的算术装置C，以及由于运算装置D而产生的增加的区域被重新创建，仅仅分配了操作A; 当由于选择器引起的增加的电路面积较小时，在提供选择器的同时将操作A分配给另一个操作B已被分配到的设备C; 并且当由于设备D而增加的电路面积较小时，重新创建设备D，以将操作A分配给重新创建的设备D.

9. 发明授权

US5010296A Wafer prober 失效
标题翻译：晶圆探测器
公开(公告)号：US5010296A
公开(公告)日：1991-04-23
申请号：US492051
申请日：1990-03-12
申请人： Kazuhisa Okada , Ichirou Kusumoto
发明人： Kazuhisa Okada , Ichirou Kusumoto
IPC分类号： G01R31/26 , G01R1/04 , G01R1/073 , G01R31/28 , H01L21/66
CPC分类号： G01R1/04 , G01R31/2886
摘要： A wafer prober includes a supporting device for supporting a wafer on which a plurality of electrode pads are disposed, a plurality of probes for contacting respective electrode pads, a spraying device for spraying a gas onto the electrode pads contacted by the plurality of probes, and an aspirating device for aspirating waste generated by the contact of the probes with the electrode pads and carried by the gas.
摘要翻译：晶片探测器包括用于支撑其上设置有多个电极焊盘的晶片的支撑装置，用于接触各个电极焊盘的多个探针，用于将气体喷射到由多个探针接触的电极焊盘上的喷射装置，以及用于吸入由探针与电极垫接触并由气体携带而产生的废物的抽吸装置。

10. 发明申请

US20110053529A1 SEMICONDUCTOR INTEGRATED CIRCUIT FOR COMMUNICATION 有权
标题翻译：半导体集成电路通信
公开(公告)号：US20110053529A1
公开(公告)日：2011-03-03
申请号：US12917135
申请日：2010-11-01
申请人： Ryoji Furuya , Kazuhisa Okada , Hiroaki Matsui
发明人： Ryoji Furuya , Kazuhisa Okada , Hiroaki Matsui
IPC分类号： H04B1/04
CPC分类号： H03D3/007 , H03C3/40 , H03D7/1433 , H04B1/406
摘要： The present invention provides a semiconductor integrated circuit for communication (RF IC) realizing high yield without deteriorating a carrier leak characteristic even when a modulation circuit is formed by using cheep parts with large variations. In a semiconductor integrated circuit (RF IC) including: an input circuit constructed by a differential amplifier circuit and a level shifter, which is provided on the ante stage of a mixer of a differential circuit called a Gilbert Cell; and a modulation circuit that performs modulation by adding an I/Q signal and a carrier wave signal, a calibration circuit for canceling a DC offset in an output of the input circuit is provided.
摘要翻译：本发明提供了一种用于通信（RF IC）的半导体集成电路，即使在通过使用具有大变化的尖峰部分形成调制电路时，也能实现高产率而不劣化载波泄漏特性。一种半导体集成电路（RF IC），包括：由差分放大电路和电平移位器构成的输入电路，其设置在称为吉尔伯特细胞的差分电路的混频器的前端; 以及通过添加I / Q信号和载波信号来执行调制的调制电路，提供了用于消除输入电路的输出中的DC偏移的校准电路。

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