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    • 1. 发明授权
    • High-level synthesis method and storage medium storing the same
    • 高级合成方法和存储介质的存储介质
    • US06604232B2
    • 2003-08-05
    • US09741057
    • 2000-12-21
    • Kazuhisa OkadaKoichi Nishida
    • Kazuhisa OkadaKoichi Nishida
    • G06F1750
    • G06F17/5045
    • A high-level synthesis method comprising the steps of converting an operating description describing one or more operations to a control data flow graph (CDFG) including one or more nodes representing the one or more operations and one or more I/O branches representing a flow of data, scheduling the CDFG obtained by the converting step, and allocating one or more logic circuits required for executing the CDFG obtained by the scheduling step. A portion of the CDFG in the converting step is subjected to logical synthesis in advance to generate a node, and the portion of the CDFG is replaced with that node.
    • 一种高级合成方法,包括以下步骤:将描述一个或多个操作的操作描述转换成包括表示所述一个或多个操作的一个或多个节点的控制数据流图(CDFG)和表示流程的一个或多个I / O分支 调度通过转换步骤获得的CDFG,并分配执行由调度步骤获得的CDFG所需的一个或多个逻辑电路。 转换步骤中的CDFG的一部分预先进行逻辑合成以生成节点,并且将该部分的CDFG替换为该节点。
    • 2. 发明授权
    • Circuit synthesis method
    • 电路合成方法
    • US06532584B1
    • 2003-03-11
    • US09709294
    • 2000-11-13
    • Koichi NishidaKazuhisa Okada
    • Koichi NishidaKazuhisa Okada
    • G06F1750
    • G06F17/5045
    • A circuit synthesis method includes the steps of converting a behavioral description describing a behavior of calculation processing into a control data flowgraph; assigning a plurality of calculations, at least one input and at least one output in the control data flowgraph into a plurality of prescribed time slots; assigning the plurality of calculations, a plurality of data dependency edges, the at least one input and the at least one output respectively to a plurality of calculation devices, at least one register, at least one input pin and at least one output pin; generating a plurality of paths corresponding to the plurality of data dependency edges; detecting a feedback loop formed of at least two of the plurality of paths and at least one of the plurality of calculation devices; and re-assigning one calculation, which has been assigned to a first calculation device included in the feedback loop, to a second calculation device among the plurality of calculation devices, so as to delete the feedback loop.
    • 电路合成方法包括将描述计算处理的行为的行为描述转换为控制数据流程图的步骤; 在控制数据流程图中分配多个计算,至少一个输入和至少一个输出到多个规定的时隙中; 将多个计算,多个数据依赖边缘,至少一个输入和至少一个输出分别分配给多个计算装置,至少一个寄存器,至少一个输入引脚和至少一个输出引脚; 产生对应于所述多个数据依赖性边缘的多个路径; 检测由所述多个路径中的至少两个路径和所述多个计算设备中的至少一个组成的反馈回路; 并将已经分配给包括在反馈回路中的第一计算装置的一个计算重新分配给多个计算装置中的第二计算装置,以便删除反馈回路。
    • 3. 发明授权
    • High level synthesis method, thread generated using the same, and method for generating circuit including such threads
    • 高级合成方法,使用其生成的线程,以及包括这种线程的电路生成方法
    • US06704914B2
    • 2004-03-09
    • US10195740
    • 2002-07-16
    • Koichi NishidaKazuhisa Okada
    • Koichi NishidaKazuhisa Okada
    • G06F1750
    • G06F17/5045
    • A high level synthesis method for generating a logic circuit of a register transfer level from an operation description includes a control data flowgraph generation stage; a scheduling stage; an allocation stage; a data path generation stage; and a control logic generation stage. When generating a thread sharing a common memory with another thread operating in parallel therewith, a memory access request is represented by a node of a control data flowgraph so as to perform scheduling, and a control logic is generated. The control logic outputs a memory access request signal to a common memory interface in a state corresponding to a step to which the node is scheduled, and keeps the state until a memory access request acceptance signal from the common memory interface is changed to be active.
    • 用于从操作描述生成寄存器传送电平的逻辑电路的高级合成方法包括控制数据流程图生成级; 调度阶段; 分配阶段 数据路径生成阶段; 和控制逻辑生成阶段。 当生成与其并行操作的另一个线程共享公共存储器的线程时,存储器访问请求由控制数据流程图的节点表示,以便执行调度,并且产生控制逻辑。 控制逻辑以对应于节点被调度的步骤的状态向公共存储器接口输出存储器访问请求信号,并保持该状态,直到来自公共存储器接口的存储器访问请求接收信号被改变为有效。
    • 4. 发明授权
    • Circuit synthesis method
    • 电路合成方法
    • US06505340B2
    • 2003-01-07
    • US09728075
    • 2000-12-04
    • Koichi NishidaKazuhisa Okada
    • Koichi NishidaKazuhisa Okada
    • G06F1750
    • G06F17/5045
    • A circuit synthesis method includes the steps of converting a behavioral description describing a behavior of calculation processing into a control data flowgraph; assigning at least one calculation, at least one input and at least one output in the control data flowgraph into prescribed time slots; assigning the at least one calculation, a plurality of data dependency edges, the at least one input and the at least one output respectively to at least one calculation device, at least one register, at least one input pin and at least one output pin; generating a plurality of paths corresponding to the plurality of data dependency edges; and detecting a first false path among the plurality of paths.
    • 电路合成方法包括将描述计算处理的行为的行为描述转换为控制数据流程图的步骤; 在控制数据流程图中将至少一个计算,至少一个输入和至少一个输出分配到规定的时隙中; 将至少一个计算,多个数据依赖性边缘,所述至少一个输入和至少一个输出分别分配给至少一个计算装置,至少一个寄存器,至少一个输入引脚和至少一个输出引脚; 产生对应于所述多个数据依赖性边缘的多个路径; 以及检测所述多个路径中的第一假路径。
    • 5. 发明申请
    • VALUABLE MEDIA HANDLING APPARATUS AND VALUABLE MEDIA HANDLING METHOD
    • 有价值的媒体处理设备和有价值的媒体处理方法
    • US20110112681A1
    • 2011-05-12
    • US12737386
    • 2008-07-09
    • Koichi NishidaKazuhiro Doi
    • Koichi NishidaKazuhiro Doi
    • G06F7/00
    • G07D11/23G07D11/30G07D11/34
    • A valuable media handling apparatus and a valuable media handling method can complete depositing operation even when a storing unit for storing valuable media becomes full of media in the course of the depositing operation. the valuable media handling apparatus has a taking-in unit to take valuable media into the apparatus, a storing unit to store the taken-in valuable media, a detecting unit to detect that the storing means is full of the valuable media or is nearly full, a returning unit to return, when the detecting unit detects that the storing nit is full of the valuable media or is nearly full while the taking-in unit is taking in the valuable media, the valuable media that are taken-in after the detection to the outside of the apparatus, an information obtaining unit to obtain the information on the valuable media taken in by the taking-in unit, and an information managing unit to manage the information on the valuable media that were taken-in until the storing unit is full of the valuable media or is nearly full as the determinate information and the information on the valuable media returned by the returning unit as the provisional determinate information.
    • 即使在存放有价介质的存储单元在存放操作过程中变得充满介质时,有价值的介质处理装置和有价值的介质处理方法也可完成存储操作。 有价值的媒体处理装置具有用于将有价值的媒体引入到装置中的购入单元,存储有价值的媒体的存储单元,检测出存储装置充满有价介质或几乎满的存储单元 当返回单元返回时,当检测单元检测到存储单元充满有价介质时,或者在接收单元处于有价介质中时几乎全满,在检测之后接收到的有价介质 信息获取单元,用于获取由所述接收单元取得的有价介质的信息;以及信息管理单元,用于管理所述有价介质的信息,直到所述存储单元 充满了有价值的媒体,或者作为确定的信息和返回单位返回的有价值媒体的信息作为临时确定信息已经足够了。
    • 8. 发明授权
    • Money processing system
    • 货币处理系统
    • US07740120B2
    • 2010-06-22
    • US11006701
    • 2004-12-08
    • Kazuyuki ShimizuHajime MurotaKazuya ItouMasashi NumakiKoichi Nishida
    • Kazuyuki ShimizuHajime MurotaKazuya ItouMasashi NumakiKoichi Nishida
    • G07D7/00G07D11/00
    • G07D11/0087G06Q40/00G07F5/24G07F19/20G07F19/203
    • A money processing system according to the present invention includes a coin change dispenser, a note change dispenser, and a control terminal, each having a control unit. The control units are generally adapted to carrying out a “change dispensing mode” control for receiving money given by a customer and dispensing change as occasion demands, and is adapted to carrying out a “money exchange mode” control, when a money exchange instruction is given from instruction means. In the money exchange mode, (a) when a single piece of money is received, a normal money exchange process for dispensing a combination of exchanged money each having a denomination smaller than that of the received money is executed such that a sum total of the combination of the exchanged money is equivalent to the received money, and (b) when a plurality of pieces of money are received, a reverse money exchange process for dispensing a combination of (the minimum number of pieces of) exchanged money each having a denomination larger than that of the received money is executed such that a sum total of the combination of the exchanged money is equivalent to the received money.
    • 根据本发明的货币处理系统包括硬币兑换分配器,纸币更换分配器和控制终端,每个具有控制单元。 控制单元通常适于执行用于接收由客户给出的货币并根据需要分配更改的“更换分配模式”控制,并且适于执行“货币兑换模式”控制,当货币兑换指令是 从指示手段给出。 在货币交换模式中,(a)当收到单笔货币时,执行用于分配具有小于接收货币的面额的兑换货币的组合的正常兑换处理,使得总计 交换的货币的组合相当于所收到的货币,(b)当收到多个货币时,用于分配具有面值的(最少数量的)交换货币的组合的反向货币兑换处理 执行大于接收到的钱的总和,使得所交换的货币的组合的总和等于所接收的货币。
    • 9. 发明申请
    • COUNTERFEIT MONEY DISCRIMINATION SUPPORT DEVICE
    • 违反货币歧视支持手段
    • US20090107800A1
    • 2009-04-30
    • US11993538
    • 2006-06-07
    • Koichi NishidaKazuyuki Shimizu
    • Koichi NishidaKazuyuki Shimizu
    • G07D5/00G07D7/00
    • G07D11/0084G07D3/16
    • The counterfeit money discrimination support device is configured to eject only the banknotes of the same denomination as a predetermined denomination of money, as specific banknotes, among banknotes taken into the device from the exterior. The denomination and quantity of the specific banknotes ejected to the exterior are stored in a memory 23. Thereafter, the specific banknotes discriminated as being not counterfeit banknotes, by hand, are then taken again into the device. When the denomination and quantity of the specific banknotes taken again into the device respectively correspond to the denomination and quantity stored in the memory 23, the discriminating operation for the counterfeit banknotes is judged to have been properly completed.
    • 假货鉴别支援装置被配置为从外部仅从作为特定纸币的纸币中取出与作为特定纸币的预定金额相同的面额的纸币。 弹出到外部的特定纸币的面额和数量被存储在存储器23中。之后,用手指定为不是伪钞的特定纸币再次被送入装置。 当再次进入设备的特定纸币的面额和数量分别对应于存储在存储器23中的面额和数量时,判断伪造纸币的识别操作已被正确完成。