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    • 3. 发明授权
    • Mute circuit
    • 静音电路
    • US07579893B2
    • 2009-08-25
    • US12099500
    • 2008-04-08
    • Kazuhiro ShimomuraMakoto Yamamoto
    • Kazuhiro ShimomuraMakoto Yamamoto
    • H03L5/00
    • H03F3/72
    • An NchMOS transistor (1) is provided for muting of an output terminal (10) to which positive and negative output signals are outputted, and a mute switch circuit (3) is provided for controlling on/off of the transistor (1) by switching a voltage applied to the gate of the transistor (1). When muting is turned off, the back gate of the transistor (1) is biased by resistance division between resistors (R1 and R2) connected in series between the output terminal (10) and a predetermined negative potential (VSS).
    • 提供NchMOS晶体管(1),用于使输出端和输出端输出的输出端子(10)静音,并设置静音开关电路(3),用于通过切换控制晶体管(1)的导通/截止 施加到晶体管(1)的栅极的电压。 当静音被关闭时,晶体管(1)的背栅通过串联连接在输出端子(10)和预定负电位(VSS)之间的电阻器(R1和R2)之间的电阻分压而偏置。
    • 4. 发明授权
    • Mute circuit
    • 静音电路
    • US07372325B2
    • 2008-05-13
    • US11492120
    • 2006-07-25
    • Kazuhiro ShimomuraMakoto Yamamoto
    • Kazuhiro ShimomuraMakoto Yamamoto
    • H03F1/14
    • H03F3/72
    • An NchMOS transistor (1) is provided for muting of an output terminal (10) to which positive and negative output signals are outputted, and a mute switch circuit (3) is provided for controlling on/off of the transistor (1) by switching a voltage applied to the gate of the transistor (1). When muting is turned off, the back gate of the transistor (1) is biased by resistance division between resistors (R1 and R2) connected in series between the output terminal (10) and a predetermined negative potential (VSS).
    • 提供NchMOS晶体管(1),用于使输出端和输出端输出的输出端子(10)静音,并设置静音开关电路(3),用于通过切换控制晶体管(1)的导通/截止 施加到晶体管(1)的栅极的电压。 当静音被关闭时,晶体管(1)的背栅极通过串联连接在输出端子(10)和预定负电位(VSS)之间的电阻器(R 1和R 2)之间的电阻分压来偏置。