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1. 发明授权

US08643065B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08643065B2
公开(公告)日：2014-02-04
申请号：US12919992
申请日：2009-12-11
申请人： Kazuhiro Fujikawa , Hideto Tamaso , Shin Harada , Yasuo Namikawa
发明人： Kazuhiro Fujikawa , Hideto Tamaso , Shin Harada , Yasuo Namikawa
IPC分类号： H01L29/80
CPC分类号： H01L29/66068 , H01L21/0465 , H01L29/1066 , H01L29/1608 , H01L29/8083
摘要： A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.
摘要翻译： JFET是半导体器件，允许更可靠地实现通过使用SiC作为材料而基本上可实现的特性，并且包括至少由碳化硅制成的上表面的晶片和形成在上表面上的栅极接触电极。晶片包括用作离子注入区域的第一p型区域，其形成为包括上表面。第一p型区域包括设置成包括上表面的基极区域和突出区域。基部区域沿着上表面的方向具有大于突出区域的宽度（w2）的宽度（w1）。栅极接触电极设置成与第一p型区域接触，使得栅极接触电极完全位于第一p型区域上，如平面图所示。

2. 发明申请

US20120119225A1 SILICON CARBIDE SUBSTRATE, EPITAXIAL LAYER PROVIDED SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE 审中-公开
标题翻译：硅碳化硅基板，外延层基板，半导体器件及制造碳化硅基板的方法
公开(公告)号：US20120119225A1
公开(公告)日：2012-05-17
申请号：US13322089
申请日：2011-02-21
申请人： Hiromu Shiomi , Hideto Tamaso , Shin Harada , Takashi Tsuno , Yasuo Namikawa
发明人： Hiromu Shiomi , Hideto Tamaso , Shin Harada , Takashi Tsuno , Yasuo Namikawa
IPC分类号： H01L29/24 , H01L21/20
CPC分类号： H01L29/7802 , H01L21/02378 , H01L21/02447 , H01L21/02529 , H01L21/02631 , H01L21/02658 , H01L21/02664 , H01L21/046 , H01L21/0495 , H01L29/04 , H01L29/1608 , H01L29/6606 , H01L29/66068
摘要： The present invention provides a silicon carbide substrate, an epitaxial layer provided substrate, a semiconductor device, and a method for manufacturing the silicon carbide substrate, each of which achieves reduced on-resistance. The silicon carbide substrate is a silicon carbide substrate having a main surface, and includes: a SiC single-crystal substrate formed in at least a portion of the main surface; and a base member disposed to surround the SiC single-crystal substrate. The base member includes a boundary region and a base region. The boundary region is adjacent to the SiC single-crystal substrate in a direction along the main surface, and has a crystal grain boundary therein. The base region is adjacent to the SiC single-crystal substrate in a direction perpendicular to the main surface, and has an impurity concentration higher than that of the SiC single-crystal substrate.
摘要翻译：本发明提供一种碳化硅衬底，提供衬底的外延层，半导体器件和制造碳化硅衬底的方法，其中每一个都实现了降低的导通电阻。碳化硅衬底是具有主表面的碳化硅衬底，并且包括：形成在主表面的至少一部分中的SiC单晶衬底; 以及设置成围绕SiC单晶衬底的基底构件。基部构件包括边界区域和基底区域。边界区域沿着主表面的方向与SiC单晶基板相邻，并且在其中具有晶界。基极区域在与主表面垂直的方向上与SiC单晶衬底相邻，杂质浓度高于SiC单晶衬底。

3. 发明申请

US20120003811A1 METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：制造半导体基板的方法
公开(公告)号：US20120003811A1
公开(公告)日：2012-01-05
申请号：US13254947
申请日：2010-09-28
申请人： Makoto Sasaki , Shin Harada , Taro Noshiguchi , Kyoto Okita , Hideto Tamaso , Yasuo Namikawa
发明人： Makoto Sasaki , Shin Harada , Taro Noshiguchi , Kyoto Okita , Hideto Tamaso , Yasuo Namikawa
IPC分类号： H01L21/04
CPC分类号： H01L21/02378 , H01L21/0243 , H01L21/02529 , H01L21/02612 , H01L21/02656 , H01L21/02667 , H01L21/047 , H01L29/66068
摘要： A first silicon carbide substrate has a first front-side surface and a first side surface. A second silicon carbide substrate has a second front-side surface and a second side surface. The second side surface is disposed such that a gap having an opening between the first and second front-side surfaces of the first and second silicon carbide substrates is disposed between the first side surface and the second side surface. A closing portion is provided to close the gap over the opening. By depositing sublimates from the first and second side surfaces onto the closing portion, a connecting portion is formed to connect the first and second side surfaces to each other so as to close the opening. After the step of forming the connecting portion, the closing portion is removed.
摘要翻译：第一碳化硅衬底具有第一前侧表面和第一侧表面。第二碳化硅衬底具有第二前侧表面和第二侧表面。第二侧表面设置成使得在第一和第二碳化硅衬底的第一和第二前侧表面之间具有开口的间隙设置在第一侧表面和第二侧表面之间。提供封闭部分以封闭开口上的间隙。通过将第一和第二侧表面的升华物沉积到封闭部分上，形成连接部分以将第一和第二侧表面彼此连接以便关闭开口。在形成连接部分的步骤之后，去除封闭部分。

4. 发明申请

US20120068195A1 METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE AND SILICON CARBIDE SUBSTRATE 审中-公开
标题翻译：制造碳化硅基体和碳化硅基体的方法
公开(公告)号：US20120068195A1
公开(公告)日：2012-03-22
申请号：US13322937
申请日：2010-09-27
申请人： Shin Harada , Makoto Sasaki , Taro Nishiguchi , Hideto Tamaso , Yasuo Namikawa
发明人： Shin Harada , Makoto Sasaki , Taro Nishiguchi , Hideto Tamaso , Yasuo Namikawa
IPC分类号： H01L29/161 , H01L21/762
CPC分类号： H01L29/7802 , C30B29/36 , H01L21/02378 , H01L21/02428 , H01L21/02433 , H01L21/02529 , H01L29/0878 , H01L29/1608 , H01L29/66068
摘要： A method for manufacturing a silicon carbide substrate includes the steps of: preparing a plurality of SiC substrates each made of single-crystal silicon carbide; forming a base layer made of silicon carbide and holding the plurality of SiC substrates, which are arranged side by side when viewed in a planar view; and forming a filling portion filling a gap between the plurality of SiC substrates.
摘要翻译：一种制造碳化硅基板的方法包括以下步骤：制备由单晶碳化硅制成的多个SiC基板; 形成由碳化硅制成的基层，并保持在俯视时并排设置的多个SiC基板; 以及形成填充所述多个SiC衬底之间的间隙的填充部分。

5. 发明申请

US20120032191A1 METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE AND SILICON CARBIDE SUBSTRATE 审中-公开
标题翻译：制造碳化硅基体和碳化硅基体的方法
公开(公告)号：US20120032191A1
公开(公告)日：2012-02-09
申请号：US13259012
申请日：2010-09-27
申请人： Shin Harada , Makoto Sasaki , Taro Nishiguchi , Hideto Tamaso , Yasuo Namikawa
发明人： Shin Harada , Makoto Sasaki , Taro Nishiguchi , Hideto Tamaso , Yasuo Namikawa
IPC分类号： H01L29/24 , H01L21/20
CPC分类号： H01L29/24 , C30B23/00 , C30B25/186 , C30B29/36 , H01L21/02378 , H01L21/02428 , H01L21/02433 , H01L21/02529 , H01L21/187 , H01L29/1608 , H01L29/66068 , H01L29/808 , H01L29/872
摘要： A method for manufacturing a silicon carbide substrate (1) having a large diameter provided readily includes the steps of: preparing a plurality of SiC substrates (20) each made of single-crystal silicon carbide; and connecting end surfaces (20B) of the plurality of SiC substrates (20) to one another such that the plurality of SiC substrates (20) are arranged side by side when viewed in a planar view.
摘要翻译：制造具有大直径的碳化硅衬底（1）的方法容易包括以下步骤：制备由单晶碳化硅制成的多个SiC衬底（20）; 并且将所述多个SiC衬底（20）的端面（20B）彼此连接，使得当在平面图中观察时所述多个SiC衬底（20）并排布置。

6. 发明申请

US20110001144A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110001144A1
公开(公告)日：2011-01-06
申请号：US12919992
申请日：2009-12-11
申请人： Kuzuhiro Fujikawa , Hideto Tamaso , Shin Harada , Yasuo Namikawa
发明人： Kuzuhiro Fujikawa , Hideto Tamaso , Shin Harada , Yasuo Namikawa
IPC分类号： H01L31/0312 , H01L21/337
CPC分类号： H01L29/66068 , H01L21/0465 , H01L29/1066 , H01L29/1608 , H01L29/8083
摘要： A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.
摘要翻译： JFET是半导体器件，允许更可靠地实现通过使用SiC作为材料而基本上可实现的特性，并且包括至少由碳化硅制成的上表面的晶片和形成在上表面上的栅极接触电极。晶片包括用作离子注入区域的第一p型区域，其形成为包括上表面。第一p型区域包括设置成包括上表面的基极区域和突出区域。基部区域沿着上表面的方向具有大于突出区域的宽度（w2）的宽度（w1）。栅极接触电极设置成与第一p型区域接触，使得栅极接触电极完全位于第一p型区域上，如平面图所示。

7. 发明申请

US20100035420A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20100035420A1
公开(公告)日：2010-02-11
申请号：US12517735
申请日：2007-11-29
申请人： Hideto Tamaso , Kazuhiro Fujikawa , Shin Harada
发明人： Hideto Tamaso , Kazuhiro Fujikawa , Shin Harada
IPC分类号： H01L21/265
CPC分类号： H01L29/7802 , H01L21/0465 , H01L29/1608 , H01L29/66068
摘要： A method of manufacturing a semiconductor device includes a first step of forming an ion implantation mask on a portion of a surface of a semiconductor; a second step of implanting ions of a first dopant into at least a portion of an exposed region of the surface of the semiconductor other than the region where the ion implantation mask is formed, to form a first dopant implantation region; a third step of, after forming the first dopant implantation region, removing a portion of the ion implantation mask to increase the exposed region of the surface of the semiconductor; and a fourth step of implanting ions of a second dopant into at least a portion of the increased exposed region of the surface of the semiconductor to form a second dopant implantation region.
摘要翻译：一种制造半导体器件的方法包括：在半导体表面的一部分上形成离子注入掩模的第一步骤; 将第一掺杂剂的离子注入除了形成离子注入掩模的区域之外的半导体表面的暴露区域的至少一部分中的第二步骤，以形成第一掺杂剂注入区域; 第三步骤，在形成第一掺杂剂注入区域之后，去除一部分离子注入掩模以增加半导体表面的暴露区域; 以及第四步骤，将第二掺杂剂的离子注入所述半导体表面的增加的暴露区域的至少一部分中，以形成第二掺杂剂注入区域。

8. 发明申请

US20100044721A1 METHOD OF PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：生产半导体器件和半导体器件的方法
公开(公告)号：US20100044721A1
公开(公告)日：2010-02-25
申请号：US12526731
申请日：2008-08-21
申请人： Kazuhiro Fujikawa , Shin Harada , Yasuo Namikawa , Takeyoshi Masuda
发明人： Kazuhiro Fujikawa , Shin Harada , Yasuo Namikawa , Takeyoshi Masuda
IPC分类号： H01L29/24 , H01L21/04
CPC分类号： H01L29/7802 , H01L21/046 , H01L21/67109 , H01L29/45 , H01L29/66068 , Y10T117/1068 , Y10T117/1088
摘要： The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 3 made of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece 61, which is a generating source other than the wafer 3.
摘要翻译：本发明提供一种制造半导体器件的方法，该半导体器件能够通过在热处理步骤中充分抑制晶片的表面粗糙化以及其中性能恶化的半导体器件来抑制由于晶片的表面粗糙而导致的性能恶化造成表面粗糙度受到抑制。制造作为半导体器件的MOSFET的方法具有制备由碳化硅制成的晶片3的步骤和通过加热晶片3进行活化退火的活化退火步骤。在活化退火步骤中，晶片3被加热在包含由除了晶片3之外的发生源的SiC片61产生的碳化硅蒸气的气氛中。

9. 发明申请

US20120056203A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120056203A1
公开(公告)日：2012-03-08
申请号：US13320250
申请日：2010-04-27
申请人： Kazuhiro Fujikawa , Shin Harada , Taro Nishiguchi , Makoto Sasaki , Yasuo Namikawa , Shinsuke Fujiwara
发明人： Kazuhiro Fujikawa , Shin Harada , Taro Nishiguchi , Makoto Sasaki , Yasuo Namikawa , Shinsuke Fujiwara
IPC分类号： H01L29/12
CPC分类号： H01L29/1608 , H01L29/32 , H01L29/66068 , H01L29/808
摘要： A JFET, which is a semiconductor device allowing for reduced manufacturing cost, includes: a silicon carbide substrate; an active layer made of single-crystal silicon carbide and disposed on one main surface of the silicon carbide substrate; a source electrode disposed on the active layer; and a drain electrode formed on the active layer and separated from the source electrode. The silicon carbide substrate includes: a base layer made of single-crystal silicon carbide, and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. The SiC layer has a defect density smaller than that of the base layer.
摘要翻译：作为允许降低制造成本的半导体器件的JFET包括：碳化硅衬底; 由单晶碳化硅构成的有源层，设置在碳化硅基板的一个主面上; 设置在所述有源层上的源电极; 以及形成在有源层上并与源电极分离的漏电极。碳化硅基板包括：由单晶碳化硅制成的基底层和由单晶碳化硅制成并设置在基底层上的SiC层。 SiC层的缺陷密度小于基底层的缺陷密度。

10. 发明申请

US20110127585A1 LATERAL JUNCTION FIELD-EFFECT TRANSISTOR 审中-公开
标题翻译：横向连接场效应晶体管
公开(公告)号：US20110127585A1
公开(公告)日：2011-06-02
申请号：US13056071
申请日：2010-03-26
申请人： Kazuhiro Fujikawa , Shin Harada , Yasuo Namikawa
发明人： Kazuhiro Fujikawa , Shin Harada , Yasuo Namikawa
IPC分类号： H01L29/80
CPC分类号： H01L29/808 , H01L29/063 , H01L29/1066 , H01L29/1608 , H01L29/66068
摘要： A lateral junction field-effect transistor capable of preventing the occurrence of leakage current and realizing a sufficient withstand voltage can be provided. In a lateral JFET according to the present invention, a buffer layer is located on a main surface of a SiC substrate and includes a p-type impurity. A channel layer is located on the buffer layer and includes an n-type impurity having a higher concentration than the concentration of the p-type impurity in the buffer layer. A source region and a drain region are of n-type and formed to be spaced from each other in a surface layer of the channel layer, and a p-type gate region is located in the surface layer of the channel layer and between the source region and the drain region. A barrier region is located in an interface region between the channel layer and the buffer layer and in a region located under the gate region and includes a p-type impurity having a higher concentration than the concentration of the p-type impurity in the buffer layer.
摘要翻译：可以提供能够防止发生漏电流并实现足够的耐压的横向结型场效应晶体管。在根据本发明的横向JFET中，缓冲层位于SiC衬底的主表面上并且包括p型杂质。沟道层位于缓冲层上，并且包括具有比缓冲层中的p型杂质浓度高的浓度的n型杂质。源极区域和漏极区域是n型并且在沟道层的表面层中形成为彼此间隔开，并且p型栅极区域位于沟道层的表面层和源极区域和漏极区域。阻挡区域位于沟道层和缓冲层之间的界面区域中，并位于栅极区域下方的区域中，并且包括具有比缓冲层中的p型杂质浓度高的浓度的p型杂质。

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